At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor device includes an oxide semiconductor transistor. The oxide semiconductor transistor includes a semiconductor...
Thin Film Transistor and Fabrication Method Thereof, Array Substrate and
A thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The thin film transistor includes: an active...
DUAL CHANNEL MEMORY
Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization...
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE
A nonvolatile semiconductor memory device according to an embodiment comprises: a tunnel insulating film disposed on a semiconductor layer; a floating gate...
CONTACT-FIRST FIELD-EFFECT TRANSISTORS
Device structures and fabrication methods for a fin-type field-effect transistor. A first contact, a second contact, and a gate electrode are formed on a fin...
PULSED LASER ANNEAL PROCESS FOR TRANSISTOR WITH PARTIAL MELT OF A RAISED
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack...
GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL
Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel...
STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS
Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate...
LOW PARASITIC CAPACITANCE AND RESISTANCE finFET DEVICE
Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate...
SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR
APPARATUS USING THE SAME AND...
A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The...
FULLY DEPLETED SILICON-ON-INSULATOR DEVICE FORMATION
A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described....
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME
A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the...
Semiconductor Device and Radio Frequency Module Formed on High Resistivity
In embodiments, a semiconductor device includes a high resistivity substrate, a transistor disposed on the high resistivity substrate, and a deep trench device...
LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
A lateral double diffused metal oxide semiconductor field-effect transistor, comprising: semiconductor substrates (400, 500), body regions (401, 501)...
SEMICONDUCTOR DEVICE USING DIAMOND
A semiconductor device includes a MISFET having: a diamond substrate; a drift layer having a first layer with a first density for providing a hopping...
PUNCH THROUGH STOPPER IN BULK FINFET DEVICE
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting...
HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND A METHOD OF FORMING THE SAME
A high electron mobility transistor (HEMT) made of nitride semiconductor materials, and a method to form the HEMT are disclosed. The HEMT includes a channel...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In a trench deeper than a thickness of a p-type base layer and configured by a first trench and a second trench, a second trench positioned at a lower portion...
POWER SEMICONDUCTOR DEVICE
In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second...
A semiconductor device includes a main IGBT region in which an IGBT is provided, a main diode region in which a diode is provided, a sense IGBT region in which...
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A first region is formed by injecting a first condition type first dopant into a surface layer portion of an IGBT section of a semiconductor substrate. A...
DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A
HIGH-RESISTANCE HANDLE WAFER
Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped...
THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY
SUBSTRATE AND DISPLAY DEVICE
A thin film transistor and manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes a source...
Recessing STI to Increase FIN Height in FIN-First Process
A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The...
FinFETs with Strained Well Regions
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having...
DOUBLE-RESURF LDMOS WITH DRIFT AND PSURF IMPLANTS SELF-ALIGNED TO A
STACKED GATE "BUMP" STRUCTURE
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field "bump" oxide region and an optional raised dielectric structure that...
Dynamic Threshold MOS and Methods of Forming the Same
A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor...
RECESSING RMG METAL GATE STACK FOR FORMING SELF-ALIGNED CONTACT
Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect...
COMPLEMENTARY GALLIUM NITRIDE INTEGRATED CIRCUITS AND METHODS OF THEIR
An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN...
QUANTUM WELL MOSFET CHANNELS HAVING LATTICE MISMATCH WITH METAL
SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS
Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a...
METHOD FOR MANUFACTURING INJECTION-ENHANCED INSULATED-GATE BIPOLAR
A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a...
TRENCH GATE POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR
Provided in the present invention is a trench gate power MOSFET (TMOS/UMOS) structure with a heavily doped polysilicon source region. The polysilicon source...
REVERSE CONDUCTION INSULATED GATE BIPOLAR TRANSISTOR (IGBT) MANUFACTURING
A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT...
METHOD FOR MANUFACTURING IGBT
A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical...
SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND
HETEROJUNCTION BIPOLAR TRANSISTOR
Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such...
METHOD FOR FORMING SPACERS FOR A TRANSISTOR GATE
A method for forming spacers of a gate of a field-effect transistor is provided, the gate being located above a layer of a semiconductor material, the method...
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate...
FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate...
Method and Structure for Metal Gates
A semiconductor device having metal gates and methods of forming the same are disclosed. The semiconductor device includes a substrate and a gate structure...
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL
JUNCTION AND DEVICES INCORPORATING...
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
Metal Gate Structure
A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first...
PROCESS FOR PRODUCING A CONTACT ON AN ACTIVE ZONE OF AN INTEGRATED
CIRCUIT, FOR EXAMPLE PRODUCED ON AN SOI...
An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as...
MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the...
CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN
Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one...
FIN SHAPE CONTACTS AND METHODS FOR FORMING FIN SHAPE CONTACTS
Semiconductor devices and methods for forming the devices with fin contacts. One method includes, for instance: obtaining a wafer with at least one isolation...
High Voltage Vertical FPMOS Fets
Semiconductor power devices such as vertical FPMOS are described having a plurality of trenches formed at a top portion of a semiconductor substrate extending...
A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a gate electrode, a first metal layer, and a second metal...
VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY
Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to...
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT INCLUDING THE DEVICE
A semiconductor device is disclosed. The semiconductor device includes a second conductive type substrate including a first first-conductive-type doping layer...