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Patent # Description
2016/0372604 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor device includes an oxide semiconductor transistor. The oxide semiconductor transistor includes a semiconductor...
2016/0372603 Thin Film Transistor and Fabrication Method Thereof, Array Substrate and Display Device
A thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The thin film transistor includes: an active...
2016/0372602 DUAL CHANNEL MEMORY
Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization...
2016/0372601 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A nonvolatile semiconductor memory device according to an embodiment comprises: a tunnel insulating film disposed on a semiconductor layer; a floating gate...
2016/0372600 CONTACT-FIRST FIELD-EFFECT TRANSISTORS
Device structures and fabrication methods for a fin-type field-effect transistor. A first contact, a second contact, and a gate electrode are formed on a fin...
2016/0372599 PULSED LASER ANNEAL PROCESS FOR TRANSISTOR WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack...
2016/0372598 GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL
Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel...
2016/0372597 STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS
Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate...
2016/0372596 LOW PARASITIC CAPACITANCE AND RESISTANCE finFET DEVICE
Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate...
2016/0372595 SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR APPARATUS USING THE SAME AND...
A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The...
2016/0372594 FULLY DEPLETED SILICON-ON-INSULATOR DEVICE FORMATION
A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described....
2016/0372593 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME
A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the...
2016/0372592 Semiconductor Device and Radio Frequency Module Formed on High Resistivity Substrate
In embodiments, a semiconductor device includes a high resistivity substrate, a transistor disposed on the high resistivity substrate, and a deep trench device...
2016/0372591 LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
A lateral double diffused metal oxide semiconductor field-effect transistor, comprising: semiconductor substrates (400, 500), body regions (401, 501)...
2016/0372590 SEMICONDUCTOR DEVICE USING DIAMOND
A semiconductor device includes a MISFET having: a diamond substrate; a drift layer having a first layer with a first density for providing a hopping...
2016/0372589 PUNCH THROUGH STOPPER IN BULK FINFET DEVICE
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting...
2016/0372588 HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND A METHOD OF FORMING THE SAME
A high electron mobility transistor (HEMT) made of nitride semiconductor materials, and a method to form the HEMT are disclosed. The HEMT includes a channel...
2016/0372587 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on...
2016/0372586 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In a trench deeper than a thickness of a p-type base layer and configured by a first trench and a second trench, a second trench positioned at a lower portion...
2016/0372585 POWER SEMICONDUCTOR DEVICE
In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second...
2016/0372584 SEMICONDUCTOR DEVICE
A semiconductor device includes a main IGBT region in which an IGBT is provided, a main diode region in which a diode is provided, a sense IGBT region in which...
2016/0372583 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A first region is formed by injecting a first condition type first dopant into a surface layer portion of an IGBT section of a semiconductor substrate. A...
2016/0372582 DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER
Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped...
2016/0372581 THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE
A thin film transistor and manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes a source...
2016/0372580 Recessing STI to Increase FIN Height in FIN-First Process
A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The...
2016/0372579 FinFETs with Strained Well Regions
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having...
2016/0372578 DOUBLE-RESURF LDMOS WITH DRIFT AND PSURF IMPLANTS SELF-ALIGNED TO A STACKED GATE "BUMP" STRUCTURE
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field "bump" oxide region and an optional raised dielectric structure that...
2016/0372577 Dynamic Threshold MOS and Methods of Forming the Same
A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor...
2016/0372576 RECESSING RMG METAL GATE STACK FOR FORMING SELF-ALIGNED CONTACT
Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect...
2016/0372575 COMPLEMENTARY GALLIUM NITRIDE INTEGRATED CIRCUITS AND METHODS OF THEIR FABRICATION
An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN...
2016/0372574 QUANTUM WELL MOSFET CHANNELS HAVING LATTICE MISMATCH WITH METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS
Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a...
2016/0372573 METHOD FOR MANUFACTURING INJECTION-ENHANCED INSULATED-GATE BIPOLAR TRANSISTOR
A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a...
2016/0372572 TRENCH GATE POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR
Provided in the present invention is a trench gate power MOSFET (TMOS/UMOS) structure with a heavily doped polysilicon source region. The polysilicon source...
2016/0372571 REVERSE CONDUCTION INSULATED GATE BIPOLAR TRANSISTOR (IGBT) MANUFACTURING METHOD
A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT...
2016/0372570 METHOD FOR MANUFACTURING IGBT
A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical...
2016/0372569 SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND HETEROJUNCTION BIPOLAR TRANSISTOR
Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such...
2016/0372568 METHOD FOR FORMING SPACERS FOR A TRANSISTOR GATE
A method for forming spacers of a gate of a field-effect transistor is provided, the gate being located above a layer of a semiconductor material, the method...
2016/0372567 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate...
2016/0372566 FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate...
2016/0372565 Method and Structure for Metal Gates
A semiconductor device having metal gates and methods of forming the same are disclosed. The semiconductor device includes a substrate and a gate structure...
2016/0372564 METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING...
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
2016/0372563 Metal Gate Structure
A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first...
2016/0372562 PROCESS FOR PRODUCING A CONTACT ON AN ACTIVE ZONE OF AN INTEGRATED CIRCUIT, FOR EXAMPLE PRODUCED ON AN SOI...
An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as...
2016/0372561 MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the...
2016/0372560 CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS
Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one...
2016/0372559 FIN SHAPE CONTACTS AND METHODS FOR FORMING FIN SHAPE CONTACTS
Semiconductor devices and methods for forming the devices with fin contacts. One method includes, for instance: obtaining a wafer with at least one isolation...
2016/0372558 High Voltage Vertical FPMOS Fets
Semiconductor power devices such as vertical FPMOS are described having a plurality of trenches formed at a top portion of a semiconductor substrate extending...
2016/0372557 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a gate electrode, a first metal layer, and a second metal...
2016/0372556 VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY
Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to...
2016/0372555 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT INCLUDING THE DEVICE
A semiconductor device is disclosed. The semiconductor device includes a second conductive type substrate including a first first-conductive-type doping layer...
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