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SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
A solid-state imaging device includes a plurality of photoelectric conversion units, a floating diffusion unit that is shared by the plurality of photoelectric...
SOLID-STATE IMAGING DEVICE AND DRIVING METHOD THEREOF, AND ELECTRONIC
The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the...
MONOLITHIC VISIBLE-INFRARED FOCAL PLANE ARRAY ON SILICON
A structure includes a silicon substrate; silicon readout circuitry disposed on a first portion of a top surface of the substrate and a radiation detecting...
THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
A thin film transistor substrate includes: a gate insulating film that covers a gate electrode and a common electrode; a transparent oxide film selectively...
ETCH CHEMISTRIES FOR METALLIZATION IN ELECTRONIC DEVICES
In various embodiments, etchants featuring (i) mixtures of hydrochloric acid, methanesulfonic acid, and nitric acid, or (ii) mixtures of phosphoric acid,...
METHOD OF MANUFACTURING ARRAY SUBSTRATE, DISPLAY SUBSTRATE, AND DISPLAY
A method of manufacturing an array substrate, a display substrate and a display device are disclosed. The method of manufacturing an array substrate comprises:...
METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE
A method of manufacturing a thin film transistor substrate includes forming a semiconductor pattern on a substrate, wherein the semiconductor pattern includes...
THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE USING THE SAME
A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a first TFT including a polycrystalline...
A semiconductor device includes a first conductive layer, a first insulating layer over the first conductive layer, first and second oxide semiconductor layers...
Dual-Gate Array Substrate, Display Panel and Display Device
A dual-gate array substrate, a display panel and a display device are provided. The dual-gate array substrate includes a plurality of pixel unit pairs arranged...
ARRAY SUBSTRATES AND THE MANUFACTURING METHOD THEREOF, AND DISPLAY PANELS
The present disclosure relates to an array substrate and the manufacturing method thereof, and a display panel. The array substrate includes a substrate and a...
DUAL CHANNEL FINFET WITH RELAXED PFET REGION
Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality...
A nitride insulating film which prevents diffusion of hydrogen into an oxide semiconductor film in a transistor including an oxide semiconductor is provided....
ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY PANEL AND
METHOD OF MANUFACTURING THE SAME, AND...
The invention discloses an array substrate, a display panel and methods of manufacturing the same, and a display device. The array substrate comprises: a pixel...
ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL
An array substrate and a manufacturing method thereof, and a display panel are provided. The array substrate comprises: a base substrate (1), including a...
Display Panel and Method of Fabricating the Same, and Display Device
The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out...
SUPPRESSING LEAKAGE CURRENTS IN A MULTI-TFT DEVICE
A technique of operating a device comprising a patterned conductor layer defining source electrode circuitry and drain electrode circuitry for a plurality of...
THIN FILM TRANSISTOR AND CIRCUIT STRUCTURE
The present disclosure provides a TFT and a circuit structure to improve the characteristics of the threshold voltage drift of the TFT. The TFT includes a gate...
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE
To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable...
FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold...
METHOD FOR MANUFACTURING A HIGH-RESISTIVITY SEMICONDUCTOR-ON-INSULATOR
A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor...
Passive Device and Radio Frequency Module Formed on High Resistivity
In embodiments, a radio frequency (RF) module includes an RF switching device, an RF active device, a passive device and a control device formed on a high...
THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE
LINE AND METHOD OF MAKING THEREOF
A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first...
NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes a first conductive layer of a first conductivity type and a second conductive layer of a second conductivity type on the...
MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
Provided is a memory device including a stack structure, a plurality of first cap layers, and a plurality of second cap layers. The stack structure is located...
METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS INCLUDING A METAL
Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of...
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND
A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium...
To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same...
Novel Dummy Gate Technology to Avoid Shorting Circuit
Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often...
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first...
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first...
METHOD TO FORM DUAL CHANNEL SEMICONDUCTOR MATERIAL FINS
A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a...
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device is provided. The semiconductor device includes a first fin-type pattern on a substrate, a first interlayer insulating layer on the...
INTEGRATED CIRCUIT HAVING DUAL MATERIAL CMOS INTEGRATION AND METHOD TO
In one aspect thereof the invention provides a structure that includes a substrate having a surface and a plurality of fins supported by the surface of the...
FET TRENCH DIPOLE FORMATION
A semiconductor structure includes a layered dipole structure formed upon a fin sidewall within a fin trench. The layered dipole structure includes a dipole...
INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source...
FIN FIELD-EFFECT TRANSISTOR GATED DIODE
The invention provides a semiconductor device. The semiconductor device includes a fin field effect transistor (finFET) array including finFET units. Each of...
Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate...
SEMICONDUCTOR DEVICE ARRANGEMENT WITH A FIRST SEMICONDUCTOR DEVICE AND
WITH A PLURALITY OF SECOND SEMICONDUCTOR...
Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a...
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING ENHANCEMENT TYPE NMOS AND
DEPRESSION TYPE MOS WITH N-TYPE...
Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a...
High Isolation Switch
An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top...
HIGH QUALITY DEEP TRENCH OXIDE
An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio...
CIRCUIT INCORPORATING MULTIPLE GATE STACK COMPOSITIONS
An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial...
DISCRETE CAPACITOR AND MANUFACTURING METHOD THEREOF
A discrete capacitor of the present invention includes a substrate having a front surface portion, an impurity diffusion layer formed on the front surface...
Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current...
Compact Electrostatic Discharge (ESD) Protection Structure
A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD)...
Electrostatic Discharge Protection Device
An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The...
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHOD FOR ELECTROSTATIC
An electrostatic discharge protection circuit is proposed comprising a series connection of a pull-up resistor and a trigger device, connecting a first and a...
SEMICONDUCTOR DEVICE HAVING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
A semiconductor device includes a first well in a substrate, a gate structure on the first well, a second well below the gate structure in the first well, a...
LOW VOLTAGE TRIGGERED SILICON CONTROLLED RECTIFIER WITH HIGH HOLDING
VOLTAGE AND SMALL SILICON AREA
A semiconductor device includes a P-type semiconductor substrate, a first N-well, a second N-well, and a P-well adjoining the first and second N-wells, a first...