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Patent # Description
2016/0372454 SEMICONDUCTOR MODULE
Control ICs for controlling IGBTs include overheat detection comparators that determine an overheated state of the case, in addition to overheat detection...
2016/0372453 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a...
2016/0372452 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED METHODS
A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a...
2016/0372451 BACK-TO-BACK SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS
Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can...
2016/0372450 FIRST-ETCHED AND LATER-PACKAGED THREE-DIMENSIONAL SYSTEM-IN-PACKAGE NORMAL CHIP STACK PACKAGE STRUCTURE AND...
A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same...
2016/0372449 INTEGRATED PASSIVE COMPONENTS IN A STACKED INTEGRATED CIRCUIT PACKAGE
Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the...
2016/0372448 SEMICONDUCTOR STRUCTURE AND A METHOD OF MAKING THEREOF
An integrated circuit package is disclosed. The integrated circuit package includes a semiconductor substrate and a TSV-less semiconductor interposer...
2016/0372447 SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME
A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first...
2016/0372446 LOW PROFILE INTEGRATED CIRCUIT (IC) PACKAGE COMPRISING A PLURALITY OF DIES
An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially...
2016/0372445 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on...
2016/0372444 INDUCTION HEATING FOR UNDERFILL REMOVAL AND CHIP REWORK
Underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate. The underfill...
2016/0372443 Method of Flip-Chip Assembly of Two Electronic Components by UV Annealing, and Assembly Obtained
The invention concerns a method of flip-chip assembly between first (1) and second (2) components each comprising connection pads (11, 21) on one of the faces...
2016/0372442 DISPLAY DEVICE
In the technical field of display, a display device for solving the technical problem of fanout mura of the pixels controlled by the wires located at both...
2016/0372441 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes: a board; a semiconductor chip that is not joined to the board; a wire whose one end is coupled with the semiconductor chip and...
2016/0372440 A SUBSTRATE LESS DIE PACKAGE HAVING WIRES WITH DIELECTRIC AND METAL COATINGS AND THE METHOD OF MANUFACTURING...
A die package having a die having a plurality of connection pads, a plurality of wire leads having metal cores with a defined core diameter, and a dielectric...
2016/0372439 Method of Manufacturing an Electronic Component
A method of manufacturing an electronic component includes applying solder paste to at least one electrically conductive portion of a package, applying a...
2016/0372438 HIGH-CONDUCTIVITY BONDING OF METAL NANOWIRE ARRAYS
A thermally-conductive and mechanically-robust bonding method for attaching a metal nanowire (MNW) array to an adjacent surface includes the steps of: removing...
2016/0372437 SEMICONDUCTOR PACKAGE
A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the...
2016/0372436 Concentric Bump Design for the Alignment in Die Stacking
An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump....
2016/0372435 SEMICONDUCTOR DEVICES WITH BALL STRENGTH IMPROVEMENT
A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally,...
2016/0372434 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding...
2016/0372433 METHODS OF FABRICATING A SEMICONDUCTOR PACKAGE
Provided is a method of fabricating a semiconductor package. The method include providing a lower package with an inner solder ball, providing a conductive...
2016/0372432 PACKAGE STRUCTURE AND METHOD THEREOF
A package structure can include: (i) a substrate having opposite first and second surfaces; (ii) a die having opposite active and back surfaces, where the die...
2016/0372431 SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second...
2016/0372430 CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT
Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed...
2016/0372429 Semiconductor Device and Radio Frequency Module Formed on High Resistivity Substrate
A semiconductor device includes a high resistivity substrate, a transistor formed on the high resistivity substrate, and a deep trench device isolation region...
2016/0372428 Semiconductor Device and Radio Frequency Module Formed on High Resistivity Substrate
A semiconductor device includes a high resistivity substrate, a first deep well region having a first conductive type and formed in the high resistivity...
2016/0372427 SEAL RING INDUCTOR AND METHOD OF FORMING THE SAME
Apparatuses and methods for providing inductance are disclosed. In one embodiment, a method for providing an inductor includes forming an electrical circuit on...
2016/0372426 Electronic Device with Redistribution Layer and Stiffeners and Related Methods
A method includes forming a molded panel that includes a number of integrated circuits, fan-out components and stiffeners embedded in an encapsulation...
2016/0372425 THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a "buffer zone" or gap layer...
2016/0372424 LOW-WARPAGE SEMICONDUCTOR SUBSTRATE AND METHOD FOR PREPARING SAME
Disclosed are a low-warpage semiconductor substrate and a method for preparing the same. The method includes: providing a first substrate and a second...
2016/0372423 PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of...
2016/0372422 Additional Etching to Increase Via Contact Area
An integrated circuit structure includes a dielectric layer, and a conductive line in the dielectric layer. The conductive line has a first top surface and a...
2016/0372421 FORMATION OF COPPER LAYER STRUCTURE WITH SELF ANNEAL STRAIN IMPROVEMENT
A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the...
2016/0372420 Damascene Thin-Film Resistor with an Added Mask Layer
In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP)...
2016/0372419 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a...
2016/0372418 SEMICONDUCTOR DEVICE
A device includes first and second semiconductor-regions located in a substrate which are adjacent to each other at a boundary. First contacts are located in...
2016/0372417 PASSIVE TUNABLE INTEGRATED CIRCUIT (PTIC) AND RELATED METHODS
A passive tunable integrated circuit (PTIC) includes a semiconductor die (die) having a plurality of barium strontium titanate (BST) tunable capacitors. The...
2016/0372416 BACKSIDE DEVICE CONTACT
A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the...
2016/0372415 SEMICONDUCTOR DEVICES
A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the...
2016/0372414 INTEGRATED CIRCUITS HAVING REDUCED DIMENSIONS BETWEEN COMPONENTS
In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit...
2016/0372413 UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS...
One method includes, among other things, forming a bi-layer etch stop layer above a conductive contact comprised of titanium nitride, the bi-layer etch stop...
2016/0372412 PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A package substrate includes: a body layer; and a pattern layer formed on a surface of the body layer. The pattern layer includes: a wire pattern; a solder pad...
2016/0372411 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package and a method of manufacturing a semiconductor package are disclosed. The semiconductor package including a first substrate including a...
2016/0372410 INTERPOSER FABRICATING PROCESS
An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an...
2016/0372409 CIRCUIT BOARD STRUCTURE
Disclosed is a circuit board structure, including the first, second and third metal layers sequentially stacked on the substrate from bottom to top and formed...
2016/0372408 METHODS OF MANUFACTURING PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE
A method of manufacturing a semiconductor package according to the present inventive concepts comprises preparing a printed circuit board (PCB) including a...
2016/0372407 WIRING BOARD AND ELECTRONIC DEVICE
This wiring board is provided with: an insulating base that has a lateral surface having an incision part; an electrode that is provided on the inner surface...
2016/0372406 Electronic Device with First and Second Contact Pads and Related Methods
An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads...
2016/0372405 SEMICONDUCTOR DEVICE PACKAGE FOR DEBUGGING AND RELATED FABRICATION METHODS
Electronic device packages and related fabrication methods are provided. An exemplary electronic device includes a semiconductor die having debug circuitry...
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