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Patent # Description
2016/0372404 INTEGRATED PACKAGE DESIGN WITH WIRE LEADS FOR PACKAGE-ON-PACKAGE PRODUCT
An integrated package design for a package-on-package product is described that uses wire leads. Some embodiments pertain to a stacked package assembly that...
2016/0372403 BUILT-UP LEAD FRAME PACKAGE AND METHOD OF MAKING THEREOF
Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The...
2016/0372402 MIXED IMPEDANCE LEADS FOR DIE PACKAGES AND METHOD OF MAKING THE SAME
A die package having mixed impedance leads where a first lead has a first metal core, and a dielectric layer surrounding the first metal core, and a second...
2016/0372401 PHOTO PATTERN METHOD TO INCREASE VIA ETCHING RATE
Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid...
2016/0372400 MULTILAYER HEAT-CONDUCTIVE SHEET, AND MANUFACTURING METHOD FOR MULTILAYER HEAT-CONDUCTIVE SHEET
Peeling due to interfacial fracture between a tack-free layer 11 and a heat-conductive layer is prevented. In the tack-free layer, an inorganic filler having a...
2016/0372399 Electrically insulating thermal interface on the discontinuity of an encapsulation structure
Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least...
2016/0372398 INTEGRATED HEAT SPREADER FOR MULTI-CHIP PACKAGES
An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive...
2016/0372397 SEMICONDUCTOR PACKAGE
The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate having a lateral surface and an...
2016/0372396 CHIP PACKAGES WITH REDUCED TEMPERATURE VARIATION
Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence...
2016/0372395 WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor device includes a semiconductor device includes an interposer having a first side and a second side opposite to the first side, wherein the...
2016/0372394 RESIN COMPOSITION FOR SEALING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE
The resin composition for sealing semiconductor according to the present invention is characterized by containing a maleimide-based compound represented by the...
2016/0372393 Laminar Structure, a Semiconductor Device and Methods for Forming Semiconductor Devices
A method for forming semiconductor devices includes placing a laminar structure having electrically insulating material arranged between a plurality of...
2016/0372392 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD
A semiconductor device fabrication method, including preparing a case having a plurality of connection terminals, and fitting a jig onto the case to protect...
2016/0372391 TIME TEMPERATURE MONITORING SYSTEM
A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active...
2016/0372390 System and Method for Test Key Characterizing Wafer Processing State
Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow...
2016/0372389 TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS
Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised...
2016/0372388 Limiting Adjustment of Polishing Rates During Substrate Polishing
A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence of characterizing values for the...
2016/0372387 Electrically Testable Microwave Integrated Circuit Packaging
An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final "non-flip chip" circuit...
2016/0372386 SUBSTRATE PROCESSING SYSTEM, METHOD OF MANAGING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH...
Provided are substrate processing systems and methods of managing the same. The method may include displaying a notification for a preventive maintenance...
2016/0372385 NON-DESTRUCTIVE DIELECTRIC LAYER THICKNESS AND DOPANT MEASURING METHOD
A semiconductor device or article includes a substrate including a feature and divided into a feature region in which the feature is formed and a pad region in...
2016/0372384 SILICON GERMANIUM FIN FORMATION VIA CONDENSATION
A method of forming a finFET device comprises forming a fin in a silicon layer of a substrate, forming a hardmask layer on a top surface of the fin, forming an...
2016/0372383 METHOD OF SOURCE/DRAIN HEIGHT CONTROL IN DUAL EPI FINFET FORMATION
A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins...
2016/0372382 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a gate structure crossing an active pattern of a substrate. The semiconductor device may include a gate dielectric pattern...
2016/0372381 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device comprises: Firstly, a semiconductor fin comprising a first sub-fin and a second sub-fin protruding from a...
2016/0372380 DUAL LINER SILICIDE
A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate...
2016/0372379 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE CONTAINING HIGH MOBILITY SEMICONDUCTOR CHANNEL MATERIALS
A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an...
2016/0372378 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The...
2016/0372377 INTEGRATED CIRCUITS WITH SELETIVE GATE ELECTRODE RECESS
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling...
2016/0372376 HIGH PERFORMANCE ISOLATED VERTICAL BIPOLAR JUNCTION TRANSISTOR AND METHOD FOR FORMING IN A CMOS INTEGRATED CIRCUIT
A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding...
2016/0372375 SUPERIMPOSED TRANSISTORS WITH AUTO-ALIGNED ACTIVE ZONE OFTHE UPPER TRANSISTOR
Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug and...
2016/0372374 Method of Electrically Isolating Leads of a Lead Frame Strip by Laser Beam Cutting
A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a...
2016/0372373 METHOD FOR PRODUCING WAVEGUIDE SUBSTRATE
To allow a metal film to have a sufficient thickness around a bottom surface of a non-through hole and prevent the metal film from being peeled from a...
2016/0372372 BACKSIDE CONTACT TO FINAL SUBSTRATE
Device structures and fabrication methods for a backside contact to a final substrate An electrically-conducting connection is formed that extends through a...
2016/0372371 METHODS FOR FORMING LOW RESISTIVITY INTERCONNECTS
Embodiments described herein generally relate to methods for forming silicide materials. Silicide materials formed according to the embodiments described...
2016/0372370 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
An insulating layer is formed on a substrate made of silicon carbide. By performing etching using a mask layer formed on the insulating layer, a contact hole...
2016/0372369 METHOD FOR FORMING INTERCONNECTS
A method of forming an interconnect composed of metallized lines and vias in a workpiece includes forming metal lines in a workpiece, with the metal lines...
2016/0372368 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a...
2016/0372367 PLATING METHOD, PLATED COMPONENT, AND PLATING SYSTEM
Reliability of a plating process and reliability of a component manufactured through the plating process can be improved by suppressing peeling between plating...
2016/0372366 INTERCONNECTS HAVING SEALING STRUCTURES TO ENABLE SELECTIVE METAL CAPPING LAYERS
Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an...
2016/0372365 METHOD FOR FORMING METAL CHALCOGENIDE THIN FILMS ON A SEMICONDUCTOR DEVICE
In some aspects, methods of forming a metal chalcogenide thin film are provided. According to some methods, a metal chalcogenide thin film is deposited on a...
2016/0372364 Bulk Layer Transfer Wafer with Multiple Etch Stop Layers
Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications...
2016/0372363 METHOD FOR MANUFACTURING BONDED SOI WAFER
The present invention is a method for manufacturing a bonded SOI wafer including: performing a thermal oxidation treatment including at least one of a thermal...
2016/0372362 METHOD FOR TRANSFERRING A THIN LAYER WITH SUPPLY OF HEAT ENERGY TO A FRAGILE ZONE VIA AN INDUCTIVE LAYER
A method of transferring a thin layer from a first substrate to a second substrate with different coefficients of thermal expansion, including: providing at...
2016/0372361 METHOD FOR PRODUCING A COMPOSITE STRUCTURE
A process for the manufacture of a composite structure includes the following stages: a) providing a donor substrate comprising a first surface and a support...
2016/0372360 SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION
A semiconductor structure is provided, which includes a semiconductor substrate, a first well region, a second well region, an active region, a shallow trench...
2016/0372359 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon...
2016/0372358 SHEET FOR SEMICONDUCTOR-RELATED-MEMBER PROCESSING AND METHOD OF MANUFACTURING CHIPS USING THE SHEET
As a semiconductor-related-member processing sheet which can stably achieve to enhance the removability of the semiconductor-related-member processing sheet...
2016/0372357 POLYIMIDE RESIN, RESIN COMPOSITION USING SAME, AND LAMINATED FILM
A polyimide resin includes an acid anhydride residue; and a diamine residue, the polyimide resin including a residue of a polysiloxane diamine represented by...
2016/0372356 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides a manufacturing technique of a semiconductor device and a display device using a peeling process, in which a transfer process...
2016/0372355 SYSTEM AND METHOD FOR REDUCING TEMPERATURE TRANSITION IN AN ELECTROSTATIC CHUCK
A system for controlling a substrate temperature in a substrate processing system includes a substrate support device, a controller, a temperature sensor, and...
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