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Provided is a semiconductor device suitable for miniaturization and higher density. The semiconductor device includes a first transistor, a second transistor...
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device (101) includes a plurality of pixel regions Pix arranged in a matrix having a row direction and a column direction, wherein each of the...
ARRAY SUBSTRATE, PREPARATION METHOD THEREOF AND DISPLAY DEVICE
The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film...
THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME
A thin film transistor substrate includes a base substrate, a first metallic layer including a gate electrode of a thin film transistor and an island electrode...
GATE ALL-AROUND FINFET DEVICE AND A METHOD OF MANUFACTURING SAME
A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin,...
CONTACT FORMATION TO 3D MONOLITHIC STACKED FINFETS
A first gate structure straddles one end of a staircase fin stack that contains a first semiconductor material fin, an insulator fin, and a second...
SELECTIVE OXIDATION FOR MAKING RELAXED SILICON GERMANIUM ON INSULATOR
Methods and devices are provided to fabricate semiconductor devices with, e.g., SiGe-on-insulator structures. For example, a method for fabricating a...
Semiconductor Device Structure With 110-PFET and 111-NFET Curent Flow
A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and...
HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE
Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench...
A display device is disclosed. In one aspect, the display device includes a substrate, a first signal line formed over the substrate and a first insulating...
DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF
An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a...
Display Substrate and Manufacturing Method Thereof, and Display Device
The present invention provides a display substrate and a manufacturing method thereof, and a display device. The display substrate comprises a base substrate,...
THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
A thin-film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate comprises an element lamination...
SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE
A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is...
TUNABLE CAPACITOR FOR FDSOI APPLICATIONS
The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried...
A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial...
Semiconductor Chip and Method for Manufacturing the Same
A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization...
DIFFERENTIAL ETCH OF METAL OXIDE BLOCKING DIELECTRIC LAYER FOR
THREE-DIMENSIONAL MEMORY DEVICES
A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over...
METHOD FOR MANUFACTURING A FINGER TRENCH CAPACITOR WITH A SPLIT-GATE FLASH
A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and...
STRUCTURE WITH EMEDDED EFS3 AND FINFET DEVICE
The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some...
REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM
A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire...
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming a storage node hole passing through an upper support layer, a bowing prevention layer and an...
Thyristor Memory Cell with Gate in Trench Adjacent the Thyristor
A volatile memory array using vertical thyristors with gates, NMOS or PMOS, in trenches adjacent the thyristors is disclosed together with methods of...
INTEGRATED CIRCUIT STRUCTURE
A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also...
Integrated Circuit Device and Method of Manufacturing the Same
An integrated circuit (IC) device includes a first-fin-type active region, a second-fin-type active region, and an inter-region stepped portion. The...
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS WITH
SUPPRESSED DOPANT DIFFUSION
A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure...
LOW NOISE AND HIGH PERFORMANCE LSI DEVICE
In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress...
INCLUDING LOW AND HIGH-VOLTAGE CMOS DEVICES IN CMOS PROCESS
A device includes a substrate, a deep well, a first well, and a second well. The deep well is formed in the substrate. The first well includes a first portion...
SEMICONDUCTOR DEVICE AND FABRICATING THE SAME
The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having...
FIN FIELD EFFECT TRANSISTOR
A fin field effect transistor (FinFET) including a first insulation region and a second insulation region and fin there between. A gate stack is disposed over...
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device is provided. The semiconductor device includes a first fin-type pattern and a second fin-type pattern formed abreast in a lengthwise...
LATERAL BIPOLAR SENSOR WITH SENSING SIGNAL AMPLIFICATION
An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar...
MANUFACTURING METHOD FOR REVERSE CONDUCTING INSULATED GATE BIPOLAR
A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for...
ULTRASONIC TRANSDUCERS IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS)
WAFERS AND RELATED APPARATUS AND METHODS
Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices....
ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL
GATE FIN-TYPE FIELD EFFECT DIODE
Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned...
FINFET WITH ESD PROTECTION
In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the...
DECOUPLING CAPACITOR CELL, CELL-BASED IC, AND PORTABLE DEVICE
A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal...
Patterned Wafer and Method of Making the Same
A patterned wafer used for production of passive-component chip bodies includes a peripheral end portion and at least one passive-component unit that including...
HYBRID SUBTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS
FOR FABRICATING SEMICONDUCTOR PACKAGES
Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may...
LAMINATED INTERPOSERS AND PACKAGES WITH EMBEDDED TRACE INTERCONNECTS
Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical...
POWER PACKAGE WITH INTEGRATED MAGNETIC FIELD SENSOR
A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a...
Package Structure and Method for Forming Same
A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the...
LIGHT EMITTING DEVICE
Embodiments of the invention provides a light emitting device, which comprises a backplane, an encapsulating structure, and a light emitting structure and a...
Multi-Wafer Stacking by Ox-Ox Bonding
A stacked semiconductor device and a method of forming the stacked semiconductor device are provided. A plurality of integrated circuits are bonded to one...
BOND PAD STRUCTURE FOR BONDING IMPROVEMENT
Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured...
SEMICONDUCTOR PACKAGE INCLUDING A STEP TYPE SUBSTRATE
Disclosed herein are semiconductor packages. A semiconductor package may include a substrate configured to include a first face and a second face opposite the...
HYBRID BOND PAD STRUCTURE
The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is...
CAVITY BRIDGE CONNECTION FOR DIE SPLIT ARCHITECTURE
An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a...
MULTILAYER SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer...