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Patent # Description
2016/0379907 DISPLAY DEVICE
A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the...
2016/0379906 DISPLAY DEVICE AND METHOD OF TESTING THE SAME
A display device includes a display panel with signal wire pads connected to data lines; an integrated circuit (IC) that feeds a data voltage to the data...
2016/0379905 METHOD FOR ESTIMATING STRESS OF ELECTRONIC COMPONENT
A method for estimating stress of an electronic component. An electronic component including first and second elements and conductive bumps is provided. Each...
2016/0379904 METHOD AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR EPITAXY STRUCTURE
A system for manufacturing semiconductor epitaxy structure includes a deposition apparatus, a curvature monitor system and a control unit. The deposition...
2016/0379903 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes etching a stack of first-material layers and second-material layers alternately disposed one on another...
2016/0379902 MEASUREMENT APPARATUS, MEASUREMENT METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A measurement apparatus according to an embodiment includes an electron emission unit and a detection unit that detects a reflection electron reflected by a...
2016/0379901 Semiconductor Devices Comprising 2D-Materials and Methods of Manufacture Thereof
A method for manufacturing a semiconductor device comprising two-dimensional (2D) materials may include: epitaxially forming a first two-dimensional (2D)...
2016/0379900 METHODS INCLUDING A PROCESSING OF WAFERS AND SPIN COATING TOOL
A method includes performing a spin coating process. In the spin coating process, a first fluid is dispensed to a surface of a wafer. The method further...
2016/0379899 IMPLEMENTING RESISTANCE DEFECT PERFORMANCE MITIGATION USING TEST SIGNATURE DIRECTED SELF HEATING AND INCREASED...
A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying...
2016/0379898 IMPLEMENTING RESISTANCE DEFECT PERFORMANCE MITIGATION USING TEST SIGNATURE DIRECTED SELF HEATING AND INCREASED...
A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying...
2016/0379897 HEAT TREATMENT APPARATUS AND TEMPERATURE CONTROL METHOD
There is provided a heat treatment apparatus for performing a predetermined film forming process on a substrate by mounting the substrate on a surface of a...
2016/0379896 PLASMA PROCESSING APPARATUS AND DATA ANALYSIS APPARATUS
In time-series data indicating light emission of plasma when plasma processing is carried out on a sample by generating the plasma, an analysis apparatus...
2016/0379895 FORMATION OF STRAINED FINS IN A FINFET DEVICE
In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a...
2016/0379894 Semiconductor Device Structure With 110-PFET and 111-NFET Current Flow Direction
A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and...
2016/0379893 INTEGRATED CIRCUIT (IC) WITH OFFSET GATE SIDEWALL CONTACTS AND METHOD OF MANUFACTURE
A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates...
2016/0379892 FINFET DEVICES
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of...
2016/0379891 WIRING STRUCTURE AND METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE
In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion...
2016/0379890 FINFET DEVICES WITH MULTIPLE CHANNEL LENGTHS
A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle...
2016/0379889 Method Of Making A Finfet Device
A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a...
2016/0379888 THE METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin...
2016/0379887 FINFET DEVICES
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of...
2016/0379886 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes forming a pre-fin extending in a first direction, the pre-fin including first, second, and third...
2016/0379885 STRUCTURES AND METHODS FOR RELIABLE PACKAGES
A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive...
2016/0379884 Method of Dicing a Wafer
A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of...
2016/0379883 INTEGRATED CIRCUIT (IC) CHIPS WITH THROUGH SILICON VIAS (TSV) AND METHOD OF FORMING THE IC
A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of...
2016/0379882 PARTIAL SPACER FOR INCREASING SELF ALIGNED CONTACT PROCESS MARGINS
A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on...
2016/0379881 INTEGRATED CIRCUITS WITH SELF ALIGNED CONTACTS AND METHODS OF MANUFACTURING THE SAME
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first...
2016/0379880 LOW RESISTANCE METAL CONTACTS TO INTERCONNECTS
A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a...
2016/0379879 TUNGSTEN FILM FORMING METHOD
In a method for forming a tungsten film, a substrate to be processed is disposed in a processing chamber having a reduced pressure atmosphere. Then a reducing...
2016/0379878 METAL LEVEL FORMATION METHOD AND AN INTEGRATED CIRCUIT STRUCTURE HAVING A METAL LEVEL WITH IMPROVED DIELECTRIC...
Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes...
2016/0379877 OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION
Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes...
2016/0379876 INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE
Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the...
2016/0379875 METHOD FOR FORMING INTERCONNECT STRUCTURE
An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower...
2016/0379874 Porogen Bonded Gap Filling Material in Semiconductor Manufacturing
A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first...
2016/0379873 HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
2016/0379872 METHOD TO PROTECT MOL METALLIZATION FROM HARDMASK STRIP PROCESS
A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including...
2016/0379871 Interconnect Structure Having an Etch Stop Layer Over Conductive Lines
A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the...
2016/0379870 SIDEWALL PROTECTION SCHEME FOR CONTACT FORMATION
Method of manufacturing a semiconductor device is described that uses sidewall protection of a recessed feature to prevent loss of critical dimension during a...
2016/0379869 LOW RESISTANCE METAL CONTACTS TO INTERCONNECTS
A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a...
2016/0379868 METHOD AND APPARATUS FOR DEPOSITING A SILICON-CONTAINING FILM
A method for depositing a silicon-containing film is performed by causing a silicon-containing gas to adsorb on a first surface of a depression formed in a...
2016/0379867 SILICON GERMANIUM-ON-INSULATOR FINFET
A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe...
2016/0379866 Isolated Semiconductor Layer Over Buried Isolation Layer
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of...
2016/0379865 METHOD FOR PREPARING SEMICONDUCTOR SUBSTRATE WITH SMOOTH EDGES
A method is provided for preparing a semiconductor substrate with smooth edges. The method includes: providing a first substrate and a second substrate;...
2016/0379864 SEMICONDUCTOR PROCESS
A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal...
2016/0379863 WAFER GRIPPER WITH NON-CONTACT SUPPORT PLATFORM
A wafer transport system includes a substantially horizontal non-contact support platform for supporting a wafer substantially horizontally at a substantially...
2016/0379862 System and Method for Adhering a Semiconductive Wafer to a Mobile Electrostatic Carrier through a Vacuum
A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive...
2016/0379861 Thermal Shield For Electrostatic Chuck
A thermal shield is disclosed that may be disposed between a heated electrostatic chuck and a base. The thermal shield comprises a thermal insulator, such as a...
2016/0379860 SiC EPITAXIAL WAFER AND METHOD FOR PRODUCING SAME, AND DEVICE FOR PRODUCING SiC EPITAXIAL WAFER
A SiC epitaxial wafer manufacturing method of the present invention includes: manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a surface...
2016/0379859 WAFER BOAT AND MANUFACTURING METHOD OF THE SAME
A wafer boat supporting a silicon wafer to be processed provides a sufficient anchor effect between a deposit film and a SiC coating film formed on a base...
2016/0379858 SUBSTRATE PROCESSING APPARATUS
A space needed to transfer a substrate container is decreased. A substrate processing apparatus includes a locating part where a substrate container...
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