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Patent # Description
2016/0378707 Vehicular intra network apparatus and client-host method of operation
A networking apparatus couples a plurality of vehicle nodes to improve bandwidth, security, and subsystem independence. The networking apparatus couples a...
2016/0378706 METHOD AND SYSTEM FOR AGGREGATION-FRIENDLY ADDRESS ASSIGNMENT TO PCIE DEVICES
A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising:...
2016/0378705 ELECTRONIC DEVICE AND METHOD FOR CONTROLLING SIGNAL STRENGTH ACCORDING TO MODE
An electronic device and a method for changing modes according to external devices connected through a universal serial bus (USB) and controlling the strength...
2016/0378704 DYNAMICALLY CONFIGURE CONNECTION MODES ON A SYSTEM BASED ON HOST DEVICE CAPABILITIES
An apparatus for configuring connection modes is described herein. The apparatus includes a plurality of ports and a processor. A first port is to couple a...
2016/0378703 MANAGEMENT OF ALLOCATION FOR ALIAS DEVICES
An input/output (I/O) request is received that indicates a priority for performing the received I/O request by a storage controller. If a base device is not...
2016/0378702 RECEIVER PACKET HANDLING
Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive...
2016/0378701 COHERENT FABRIC INTERCONNECT FOR USE IN MULTIPLE TOPOLOGIES
An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus...
2016/0378700 NON-INTERFERING TRANSACTIONS
Embodiments relate to non-interfering transactions. An aspect includes receiving, by a first transaction, a conflicting remote access request from a requester,...
2016/0378699 IMPLEMENTING PSEUDO NON-MASKING INTERRUPTS BEHAVIOR USING A PRIORITY INTERRUPT CONTROLLER
A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable...
2016/0378698 INSTRUCTION AND LOGIC FOR REAL-TIME BEHAVIOR OF INTERRUPTS
A processor includes a core and an interrupt control unit. The core includes logic to handle an interrupt. The interrupt control unit includes logic to receive...
2016/0378697 PROVIDING DEDICATED RESOURCES FOR A SYSTEM MANAGEMENT MODE OF A PROCESSOR
In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be...
2016/0378696 EXPOSING MEMORY-MAPPED IO DEVICES TO DRIVERS BY EMULATING PCI BUS AND PCI DEVICE CONFIGURATION SPACE
Devices are emulated as PCI devices so that existing PCI drivers can be used for the devices. This is accomplished by creating a shim PCI device with a...
2016/0378695 Systems And Methods For Asymmetric Memory Access To Memory Banks Within Integrated Circuit Systems
Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory...
2016/0378694 MANAGEMENT OF ALLOCATION FOR ALIAS DEVICES
Embodiments of the present invention provide systems, methods, and computer program products for managing computing devices to handle an input/output (I/O)...
2016/0378693 INFORMATION PROCESSING APPARATUS AND PROGRAM EXECUTION METHOD
According to one embodiment, an information processing apparatus includes a processor and a memory. The processor operates in a first state and a second state....
2016/0378692 Instructions and Logic to Provide Memory Access Key Protection Functionality
Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A...
2016/0378691 SYSTEM, APPARATUS AND METHOD FOR PROTECTING A STORAGE AGAINST AN ATTACK
In one embodiment, an apparatus includes a storage controller to couple to a storage device. The storage controller may include a first counter to maintain a...
2016/0378690 SYSTEM AND METHODS FOR EXECUTING ENCRYPTED CODE
The present disclosure relates systems and methods for executing an encrypted code section in a shieldable CPU memory cache. Functional characteristics of the...
2016/0378689 SYSTEMS AND METHODS FOR SECURE MULTI-TENANT DATA STORAGE
Systems and methods are provided for transmitting data for secure storage. For each of two or more data sets, a plurality of shares are generated containing a...
2016/0378688 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO SUPPORT LIVE MIGRATION OF PROTECTED CONTAINERS
A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the...
2016/0378687 TECHNOLOGIES FOR MEMORY CONFIDENTIALITY, INTEGRITY, AND REPLAY PROTECTION
Technologies for memory encryption include a computing device to generate a keyed hash of a data line based on a statistical counter value and a memory address...
2016/0378686 MEMORY ENCRYPTION EXCLUSION METHOD AND APPARATUS
Apparatuses, methods and storage medium associated with memory encryption exclusion are disclosed herein. In embodiments, an apparatus may include one or more...
2016/0378685 VIRTUALIZED TRUSTED STORAGE
Particular embodiments described herein provide for an electronic device that can be configured to receive a request from a process to access data is a system,...
2016/0378684 MULTI-PAGE CHECK HINTS FOR SELECTIVE CHECKING OF PROTECTED CONTAINER PAGE VERSUS REGULAR PAGE TYPE INDICATIONS...
A processor of an aspect includes at least one translation lookaside buffer (TLB) and a memory management unit (MMU). Each TLB is to store translations of...
2016/0378683 64KB Page System that Supports 4KB Page Operations
In an embodiment, a processor includes logic to provide a first virtual address of first data stored in a memory at a first physical address. The memory...
2016/0378682 ACCESS LOG AND ADDRESS TRANSLATION LOG FOR A PROCESSOR
A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses...
2016/0378681 PAGE COMPRESSION STRATEGY FOR IMPROVED PAGE OUT PROCESS
A page compression strategy classifies uncompressed pages selected for compression. Similarly classified pages are compressed and bound into a single logical...
2016/0378680 FILE ACCESS METHOD AND RELATED DEVICE
Embodiments of the application provide a file access method. A computing node receives a file open request that carries a file identifier. The computing node...
2016/0378679 TECHNOLOGIES FOR POSITION-INDEPENDENT PERSISTENT MEMORY POINTERS
Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The...
2016/0378678 DYNAMIC PAGE TABLE EDIT CONTROL
Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page...
2016/0378677 EVENT SPECIFIC PAGE FAULTS FOR INTERRUPT HANDLING
Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution...
2016/0378676 METHODS AND APPARATUS TO RE-DIRECT DETECTED ACCESS REQUESTS IN A MODULARIZED VIRTUALIZATION TOPOLOGY USING...
Methods, apparatus are articles of manufacture are disclosed to re-direct detected access requests in a modularized virtualization topology using virtual hard...
2016/0378675 GENERATING DATA TABLES
The method includes identifying a first data table that includes a set of rows and a structure. The method further includes creating a second data table and a...
2016/0378674 SHARED VIRTUAL ADDRESS SPACE FOR HETEROGENEOUS PROCESSORS
A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for...
2016/0378673 Hybrid Tracking of Transaction Read and Write Sets
Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both ...
2016/0378672 HARDWARE APPARATUSES AND METHODS FOR DISTRIBUTED DURABLE AND ATOMIC TRANSACTIONS IN NON-VOLATILE MEMORY
Hardware apparatuses and methods for distributed durable and atomic transactions in non-volatile memory are described. In one embodiment, a hardware apparatus...
2016/0378671 CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM
A cache memory includes a first cache memory that is accessible per cache line, and a second cache memory that is accessible per word, the second cache memory...
2016/0378670 DYNAMIC STRUCTURAL MANAGEMENT OF A DISTRIBUTED CACHING INFRASTRUCTURE
Embodiments of the present invention provide a method, system and computer program product for the dynamic structural management of an n-Tier distributed...
2016/0378669 MULTIPLE WINDOW BASED SEGMENT PREFETCHING
A method, a computer program product, and a computer system for implementing multiple window based segment prefetch used for data pages that are out of...
2016/0378668 MEMORY MODULE WITH EMBEDDED ACCESS METADATA
A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the...
2016/0378667 INDEPENDENT BETWEEN-MODULE PREFETCHING FOR PROCESSOR MEMORY MODULES
A processor employs multiple prefetchers at a processor to identify patterns in memory accesses to different memory modules. The memory accesses can include...
2016/0378666 CLIENT VOTING-INCLUSIVE IN-MEMORY DATA GRID (IMDG) CACHE MANAGEMENT
A client application cache access profile is created that documents accesses over time to data cached within an in-memory data grid (IMDG) cache by each of a...
2016/0378665 TECHNOLOGIES FOR PREDICTIVE FILE CACHING AND SYNCHRONIZATION
Technologies for predictive caching include a computing device to receive sensor data generated by one or more sensors of the computing device and determine a...
2016/0378664 SUPPORTING FAULT INFORMATION DELIVERY
A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit...
2016/0378663 SYSTEM OPERATION QUEUE FOR TRANSACTION
Embodiments relate to a system operation queue for a transaction. An aspect includes determining whether a system operation is part of an in-progress...
2016/0378662 Hybrid Tracking of Transaction Read and Write Sets
Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both...
2016/0378661 INSTRUCTION BLOCK ALLOCATION
Apparatus and methods are disclosed for throttling processor operation in block-based processor architectures. In one example of the disclosed technology, a...
2016/0378660 FLUSHING AND RESTORING CORE MEMORY CONTENT TO EXTERNAL MEMORY
A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the...
2016/0378659 Hybrid Tracking of Transaction Read and Write Sets
Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both...
2016/0378658 Hybrid Tracking of Transaction Read and Write Sets
Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both ...
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