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Patent # Description
2016/0378507 FIRMWARE BLOCK DISPATCH BASED ON FUSING
The present disclosure is directed to firmware block dispatch based on fusing. A device may determine firmware blocks to load during initialization of the...
2016/0378506 EFFICIENT POWER MANAGEMENT OF A SYSTEM WITH VIRTUAL MACHINES
Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of...
2016/0378505 SYSTEM OPERATION QUEUE FOR TRANSACTION
Embodiments relate to a system operation queue for a transaction. An aspect includes determining whether a system operation is part of an in-progress...
2016/0378504 TECHNIQUES TO WAKE-UP DEPENDENT INSTRUCTIONS FOR BACK-TO-BACK ISSUE IN A MICROPROCESSOR
Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue...
2016/0378503 TECHNIQUES TO WAKE-UP DEPENDENT INSTRUCTIONS FOR BACK-TO-BACK ISSUE IN A MICROPROCESSOR
Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue...
2016/0378502 AGE-BASED MANAGEMENT OF INSTRUCTION BLOCKS IN A PROCESSOR INSTRUCTION WINDOW
A processor core in an instruction block-based microarchitecture includes a control unit that explicitly tracks instruction block state including age or...
2016/0378501 SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT
A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the...
2016/0378500 SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT
A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the...
2016/0378499 VERIFYING BRANCH TARGETS
Apparatus and methods are disclosed for implementing bad jump detection in block-based processor architectures. In one example of the disclosed technology, a...
2016/0378498 Systems, Methods, and Apparatuses for Last Branch Record Support
Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit...
2016/0378497 Systems, Methods, and Apparatuses for Thread Selection and Reservation Station Binding
Embodiments of systems, methods, and apparatuses for thread selection and reservation station binding are disclosed. In an embodiment, an apparatus includes...
2016/0378496 Explicit Instruction Scheduler State Information for a Processor
A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor, is provided. The...
2016/0378495 Locking Operand Values for Groups of Instructions Executed Atomically
A method including fetching a group of instructions, including a group header for the group of instructions, where the group of instructions is configured to...
2016/0378494 Processing Encoding Format to Interpret Information Regarding a Group of Instructions
A method including fetching information regarding a group of instructions, where the group of instructions is configured to execute atomically by a processor,...
2016/0378493 BULK ALLOCATION OF INSTRUCTION BLOCKS TO A PROCESSOR INSTRUCTION WINDOW
A processor core in an instruction block-based microarchitecture includes a control unit that allocates instructions into an instruction window in bulk by...
2016/0378492 Decoding Information About a Group of Instructions Including a Size of the Group of Instructions
A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor is provided. The method...
2016/0378491 DETERMINATION OF TARGET LOCATION FOR TRANSFER OF PROCESSOR CONTROL
Methods and apparatus are disclosed for eliminating explicit control flow instructions (for example, branch instructions) from atomic instruction blocks...
2016/0378490 PROTECTING CONFIDENTIAL DATA WITH TRANSACTIONAL PROCESSING IN EXECUTE-ONLY MEMORY
Generally, this disclosure provides systems, devices, methods and computer readable media for protecting confidential data with transactional processing in...
2016/0378489 REGISTER FILE MAPPING
An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a...
2016/0378488 ACCESS TO TARGET ADDRESS
Systems, methods, and computer-readable storage are disclosed for providing early access to target addresses in block-based processor architectures. In one...
2016/0378487 EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART
A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction...
2016/0378486 METHOD AND APPARATUS FOR EXECUTION MODE SELECTION
An apparatus and method for performing high performance instruction emulation. For example, one embodiment of the invention includes a processor to process an...
2016/0378485 EFFICIENT QUANTIZATION OF COMPARE RESULTS
A set machine instruction is provided that has associated therewith a result location to be used with a set operation. The set machine instruction is executed,...
2016/0378484 MAPPING INSTRUCTION BLOCKS BASED ON BLOCK SIZE
A processor core in an instruction block-based microarchitecture utilizes instruction blocks having headers that include an index to a size table that may be...
2016/0378483 REUSE OF DECODED INSTRUCTIONS
Systems and methods are disclosed for reusing fetched and decoded instructions in block-based processor architectures. In one example of the disclosed...
2016/0378482 EFFICIENT QUANTIZATION OF COMPARE RESULTS
A set machine instruction is provided that has associated therewith a result location to be used with a set operation. The set machine instruction is executed,...
2016/0378481 INSTRUCTION AND LOGIC FOR ENCODED WORD INSTRUCTION COMPRESSION
A processor includes a memory and a decompressor. The memory is to store compressed instruction. The decompressor includes logic to receive a request for an...
2016/0378480 Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations
Embodiments for systems, methods, and apparatuses for improving performance of status dependent computations are detailed. In an embodiment, an hardware...
2016/0378479 DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER
A processor core in an instruction block-based microarchitecture is configured so that an instruction window and operand buffers are decoupled for independent...
2016/0378478 INSTRUCTIONS TO COUNT CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES
A machine instruction to find a condition location within registers, such as vector registers. The machine instruction has associated therewith a register to...
2016/0378477 INSTRUCTIONS TO COUNT CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES
A machine instruction to find a condition location within registers, such as vector registers. The machine instruction has associated therewith a register to...
2016/0378476 NON-DEFAULT INSTRUCTION HANDLING WITHIN TRANSACTION
Embodiments relate to non-default instruction handling within a transaction. An aspect includes entering a transaction, the transaction comprising a first...
2016/0378475 INSTRUCTION TO PERFORM A LOGICAL OPERATION ON CONDITIONS AND TO QUANTIZE THE BOOLEAN RESULT OF THAT OPERATION
A machine instruction is provided that has associated therewith a result location to be used for a set operation, a first source, a second source, and an...
2016/0378474 CONVERSION OF BOOLEAN CONDITIONS
A Set Boolean machine instruction is provided that has associated therewith a result location to be used for a set Boolean operation and a mask. The mask is...
2016/0378473 INSTRUCTION AND LOGIC FOR CHARACTERIZATION OF DATA ACCESS
A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit...
2016/0378472 Instruction and Logic for Predication and Implicit Destination
A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a...
2016/0378471 INSTRUCTION AND LOGIC FOR EXECUTION CONTEXT GROUPS FOR PARALLEL PROCESSING
A processor includes cores and a context management circuit. The circuit includes logic to determine an execution context group (ECG) to be migrated between...
2016/0378470 INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS
A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive...
2016/0378469 INSTRUCTION TO PERFORM A LOGICAL OPERATION ON CONDITIONS AND TO QUANTIZE THE BOOLEAN RESULT OF THAT OPERATION
A machine instruction is provided that has associated therewith a result location to be used for a set operation, a first source, a second source, and an...
2016/0378468 CONVERSION OF BOOLEAN CONDITIONS
A Set Boolean machine instruction is provided that has associated therewith a result location to be used for a set Boolean operation and a mask. The mask is...
2016/0378467 PERSISTENT COMMIT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
A processor includes at least one memory controller, and a decode unit to decode a persistent commit demarcate instruction. The persistent commit demarcate...
2016/0378466 APPARATUS AND METHOD FOR EFFICIENT CALL/RETURN EMULATION USING A DUAL RETURN STACK BUFFER
An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. For example, one embodiment of a processor comprises: a...
2016/0378465 EFFICIENT SPARSE ARRAY HANDLING IN A PROCESSOR
In one embodiment, a processor includes at least one core to execute instructions and an accelerator coupled to the at least one core. The accelerator may...
2016/0378464 DATA EXTRACTION AND GENERATION TOOL
An item to be processed is received and scanned. The scan identifies any functions or procedures in the item being processed, and extracts actual code...
2016/0378463 SELECTIVE NOTIFICATIONS ACCORDING TO MERGE DISTANCE FOR SOFTWARE VERSION BRANCHES WITHIN A SOFTWARE...
A computer-implemented method of controlling version branching within a software configuration management system (SCMS) can include, responsive to a user...
2016/0378462 Method, Apparatus, and System for Implementing JAVA Application Installation by Means of Cloud Compilation
Embodiments of the present disclosure disclose a method for implementing JAVA application program installation by cloud compilation, including sending, by a...
2016/0378461 APPLICATION DATA SYNCHRONIZATION METHOD AND APPARATUS
The present invention discloses an application data synchronization method and an apparatus. When a first operating system and a second operating system are...
2016/0378460 PARTIALLY RECONFIGURING ACCELERATION COMPONENTS
Aspects extend to methods, systems, and computer program products for partially reconfiguring acceleration components. Partial reconfiguration can be...
2016/0378459 SYSTEMS MANAGEMENT BASED ON SEMANTIC MODELS AND LOW-LEVEL RUNTIME STATE
Various embodiments manage deployable computing environments. In one embodiment, a semantic model of a computing environment is analyzed. The computing...
2016/0378458 METHOD AND DEVICE FOR SYSTEM APPLICATION INSTALLATION PACKAGE, AND TERMINAL
The embodiments of disclosure provide a method and device for loading a system Application (APP) installation package, and a terminal. The method includes...
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