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Patent # Description
2017/0005105 Height Reduction in Memory Periphery
A NAND flash memory has word lines in a memory array area and contact pads and lead lines in a word line hookup area, each of the word lines connected to a...
2017/0005104 SHALLOW TRENCH AIR GAPS AND THEIR FORMATION
A method of forming a NAND flash memory includes etching between word lines to expose isolation material in shallow trench isolation (STI) trenches while...
2017/0005103 One Time Programmable Memory with a Twin Gate Structure
A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having...
2017/0005102 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and...
2017/0005101 INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME
Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC...
2017/0005100 SEMICONDUCTOR DEVICE INCLUDING DUMMY METAL
A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of...
2017/0005099 METHODS OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on...
2017/0005098 STRUCTURE AND METHOD TO PREVENT EPI SHORT BETWEEN TRENCHES IN FINFET EDRAM
After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench...
2017/0005097 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact...
2017/0005096 SUB WORD LINE DRIVER OF A SEMICONDUCTOR MEMORY DEVICE
A sub word line driver of a semiconductor memory device including a sub word line driver is disclosed. The sub word line driver of a semiconductor memory...
2017/0005095 SANDWICH EPI CHANNEL FOR DEVICE ENHANCEMENT
The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that...
2017/0005094 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active...
2017/0005093 Semiconductor Device with Split Work Functions
A field effect transistor (FET) configuration is provided having a gate region with a split work function for the source-side and drain-side of the gate...
2017/0005092 LOW END PARASITIC CAPACITANCE FINFET
Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with...
2017/0005091 Semiconductor Devices and Method for Forming Semiconductor Devices
A semiconductor device includes a semiconductor laminar structure arranged on a semiconductor substrate. The semiconductor laminar structure includes a first...
2017/0005090 FINFET with U-Shaped Channel
In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on...
2017/0005089 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME
In a non-insulated DC-DC converter having a circuit in which a power MOS.cndot.FET high-side switch and a power MOS.cndot.FET low-side switch are connected in...
2017/0005088 DISTRIBUTED DECOUPLING CAPACITOR
An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one...
2017/0005087 DISTRIBUTED DECOUPLING CAPACITOR
The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one...
2017/0005086 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT INCLUDING THE SAME
A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the...
2017/0005085 LATERAL BICMOS REPLACEMENT METAL GATE
A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first...
2017/0005084 PROTECTIVE CIRCUIT FOR CATHODE LAYER, PROTECTIVE METHOD AND OLED DISPLAY DEVICE
A protective circuit for a cathode layer, a protective method and an OLED display device are provided. The protective circuit includes a power supply, and an...
2017/0005083 DISPLAY DEVICE
A structure of connecting a panel driver to a side of a display panel and an electrostatic discharge (ESD) structure are discussed. The display device...
2017/0005082 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor device is provided. The method includes providing a substrate; forming a well region on the substrate; forming at...
2017/0005081 ESD PROTECTION STRUCTURE
An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well...
2017/0005080 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed...
2017/0005079 METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR DEVICES AND OPTOELECTRONIC SEMICONDUCTOR DEVICE
A method for producing a plurality of optoelectronic semiconductor components (100) is provided, comprising the following steps: a) providing an auxiliary...
2017/0005078 LIGHT EMITTING DEVICE
A light emitting device includes a base with a light transmissivity, a first light emitting element which has an electrode formed on only one surface, the...
2017/0005077 Electronic Devices With Soft Input-Output Components
An electronic device may have control circuitry coupled to input-output devices such as a display. A flexible input-output device may be formed from an...
2017/0005076 Stacked Integrated Circuits with Redistribution Lines
An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality...
2017/0005075 SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the...
2017/0005074 3D PACKAGE STRUCTURE AND METHODS OF FORMING SAME
An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first...
2017/0005073 3DIC Stacking Device and Method of Manufacture
A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a...
2017/0005072 STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE
Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip...
2017/0005071 STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE
Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the...
2017/0005070 Method of manufacturing a semiconductor package
Methods for a semiconductor device package formed in a chip-on-wafer last process using thin film adhesives are disclosed and may include bonding a first...
2017/0005069 Wafer Backside Interconnect Structure Connected to TSVs
An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the ...
2017/0005068 THREE-DIMENSIONAL MOUNTING METHOD AND THREE-DIMENSIONAL MOUNTING DEVICE
A three-dimensional mounting method for successively laminating N number of upper-layer joining materials includes positioning a first upper-layer joining...
2017/0005067 Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a...
2017/0005066 METHOD OF MANUFACTURING A FUNCTIONAL INLAY
The method of manufacturing a functional inlay comprises the steps of: a support layer with at least a first and a second side a wire antenna in said support...
2017/0005065 BONDING DEVICE
[Problem] To provide a bonding device capable of adequately controlling a leading end of a capillary when a ball formed at a leading end of a wire is pressed...
2017/0005064 BONDING DEVICE
[Problem] To provide a bonding device in which a capillary can perform stable vibration from a low frequency to a high frequency while achieving lightening...
2017/0005063 REFLOW APPARATUS
A reflow apparatus include a carrier supporting a printed circuit board placed on a side thereof by using a vacuum pressure generated therein, and a processing...
2017/0005062 DIE-BONDING LAYER FORMATION FILM, PROCESSED PRODUCT HAVING DIE-BONDING LAYER FORMATION FILM ATTACHED THERETO,...
A die-bonding layer formation film to be used for fixing a processed product to an adherend, includes an adhesive layer, wherein, the storage elastic modulus...
2017/0005061 SEMI-CONDUCTOR PACKAGE STRUCTURE
Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts,...
2017/0005060 PACKAGING DEVICE AND METHOD OF MAKING THE SAME
The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace...
2017/0005059 Bump-on-Trace Structures with High Assembly Yield
A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace...
2017/0005058 CHIP PACKAGE
An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads...
2017/0005057 CHIP PACKAGE
An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer...
2017/0005056 SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit ("IC") package substrate capable of...
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