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SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a...
POST-PASSIVATION INTERCONNECT STRUCTURE AND METHODS THEREOF
The semiconductor device includes a die that contains a substrate and a bond pad. A connective layer is disposed over the die. The connective layer includes a...
CHIP MOUNTING STRUCTURE
Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so...
UNDER BUMP METALLURGY (UBM) AND METHODS OF FORMING SAME
A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises...
Semiconductor Device And Bump Formation Process
A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the...
CHIP WITH I/O PADS ON PERIPHERIES AND METHOD MAKING THE SAME
A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the...
Semiconductor Package System and Method
A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die...
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of...
ELECTRONIC APPARATUS OPERABLE IN HIGH FREQUENCIES
An electronic apparatus that includes a semiconductor device mounted on an assembly base is disclosed. The semiconductor device includes a transmission line,...
ISOLATOR AND METHOD OF MANUFACTURING ISOLATOR
An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a...
SEMICONDUCTOR DEVICE AND METHOD
Disclosed is a semiconductor device comprising a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive...
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
The present invention is to provide a semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a...
INTEGRATED CIRCUIT (IC) INCLUDING SEMICONDUCTOR RESISTOR AND RESISTANCE
COMPENSATION CIRCUIT AND RELATED METHODS
An integrated circuit (IC) may include a semiconductor substrate, and a semiconductor resistor. The semiconductor resistor may include a well in the...
SEMICONDUCTOR DEVICE PACKAGES
The present disclosure relates to a semiconductor device package and a method for manufacturing the semiconductor device package. The semiconductor device...
METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC
The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method...
ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL
NITRIDE LINERS AND CAPS FOR COPPER LOW...
An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting...
SELF-FORMING BARRIER FOR SUBTRACTIVE COPPER
A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a...
CVD METAL SEED LAYER
The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In...
METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON
MULTILAYERED METAL CONTACTS, AND...
A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a...
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
As means for preventing a leakage of a fuse element cut by laser trimming due to a conductive residue or the like, an insulating film which has a high thermal...
Stacked Semiconductor Devices and Methods of Forming Same
Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the...
Provided is a package structure including a die, an encapsulant, a through via, a first dielectric layer, a conductive line structure, an adhesion promotion...
SUBSTRATE, LIGHT-EMITTING DEVICE WITH SUBSTRATE, METHOD OF MANUFACTURING
SUBSTRATE ASSEMBLY AND METHOD OF...
A substrate includes a first electrode layer including a first electrode and a second electrode; a second electrode layer including a first electrode and a...
LEAD FRAME AND STACK PACKAGE MODULE INCLUDING THE SAME
A lead frame and a stack package module including the same are provided. The lead frame including a lower-end coupling portion coupled to a lower package...
SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND
SEMICONDUCTOR DEVICE MOUNTING STRUCTURE
A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections,...
Flat No-Leads Package With Improved Contact Pins
According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an...
METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE HAVING A MULTI-LAYER
ENCAPSULATED CONDUCTIVE SUBSTRATE AND STRUCTURE
In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated...
LEADFRAME PACKAGE WITH STABLE EXTENDED LEADS
Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead...
3D Chip-On-Wafer-On-Substrate Structure With Via Last Process
Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second...
NANOPARTICLE THERMAL INTERFACE AGENTS FOR REDUCING THERMAL CONDUCTANCE
A thermal interface material (TIM) using high thermal conductivity nano-particles, particularly ones with large aspect ratios, for enhancing thermal transport...
Electronic device and method of manufacturing the same
Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an...
Provided is a semiconductor device that includes a passivation film thinner than a wiring layer and has a high resistance to a stress caused during bonding. In...
ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first...
PACKAGING STRUCTURE, PACKAGING METHOD AND TEMPLATE USED IN PACKAGING
Disclosed are a packaging structure, a packaging method and a template used in packaging method. The packaging structure comprises: a substrate; a chip mounted...
EPOXY RESIN COMPOSITION, SEMICONDUCTOR SEALING AGENT, AND SEMICONDUCTOR
An epoxy resin composition includes: (A) epoxy resin; (B) a curing agent; (C) 0.1 to 10 mass % of silica filler with an average particle size of 10 nm or more...
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A sample semiconductor device is manufactured and the curvature of the sample is measured. An area is set to be removed from an encapsulation resin layer on...
SEMICONDUCTOR WAFER PROCESSING METHODS AND APPARATUS
A semiconductor wafer processing method comprising controlling the temperature of a semiconductor wafer to be within a predetermined processing temperature...
METHOD AND DEVICE FOR INSPECTION OF A SEMICONDUCTOR DEVICE
A method for inspection of a semiconductor device is disclosed. In one aspect, the method includes performing a processing step in manufacturing of the...
DETECTION APPARATUS, LITHOGRAPHY APPARATUS, METHOD OF MANUFACTURING
ARTICLE, AND DETECTION METHOD
The present invention provides a detection apparatus which detects a position of a mark on a substrate, the apparatus comprising an image capturing unit having...
PROTECTIVE FILM-FORMING FILM, SHEET FOR FORMING PROTECTIVE FILM, COMPLEX
SHEET FOR FORMING PROTECTIVE FILM, AND...
Provided is a sheet (2) for forming protective film, including: a protective film-forming film (1) characterized in that the light transmittance thereof at a...
MONITOR PROCESS FOR LITHOGRAPHY AND ETCHING PROCESSES
A monitor process for lithography and etching processes includes the following steps. A first lithography process and a first etching process are performed to...
TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION
REGIONS AND LOCAL TRENCH ISOLATION REGIONS
Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a...
Workpiece Processing Technique
Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the...
STACKED SHORT AND LONG CHANNEL FINFETS
An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an...
FINFET Devices and Methods of Forming
In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a...
Germanium-Based CMOS Comprising Silicon Cap Formed Over PMOS Region Having
A Thickness Less Than That Over NMOS...
A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the...
MOSFET DEVICES WITH ASYMMETRIC STRUCTURAL CONFIGURATIONS INTRODUCING
DIFFERENT ELECTRICAL CHARACTERISTICS
First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a...
SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE AND METHOD FOR FABRICATING THE
A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a...
A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a...
GATE STACK FORMED WITH INTERRUPTED DEPOSITION PROCESSES AND LASER
Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure...