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Patent # Description
2017/0012067 INVISIBLE LIGHT FLAT PLATE DETECTOR AND MANUFACTURING METHOD THEREOF, IMAGING APPARATUS
The present invention provides an invisible light flat plate detector and a manufacturing method thereof, an imaging apparatus, relates to the field of...
2017/0012066 IMAGE SENSOR HAVING CONVERSION DEVICE ISOLATION LAYER DISPOSED IN PHOTOELECTRIC CONVERSION DEVICE
An image sensor includes a first conductivity type first impurity region surrounded by a pixel isolation layer surrounds; a first conversion device isolation...
2017/0012065 ARRAY SUBSTRATE, A METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
The present invention provides an array substrate, a method for manufacturing the same, and a display device including the same. In the manufacturing method of...
2017/0012064 SiON GRADIENT CONCEPT
Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid...
2017/0012063 ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME
An array substrate includes a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer...
2017/0012062 SEMICONDUCTOR DEVICE
A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device...
2017/0012061 BRIDGING LOCAL SEMICONDUCTOR INTERCONNECTS
A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS...
2017/0012060 Array Substrate and Manufacturing Method Thereof, Display Device
A manufacturing method of an array substrate is disclosed. The manufacturing method includes a step of forming a pattern including a pixel electrode; and the...
2017/0012059 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY APPARATUS
The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate comprises a gate layer, a...
2017/0012058 Array Substrate and Manufacturing Method Thereof, Display Device
An array substrate and manufacturing method thereof, a display device are provided. The array substrate includes a display region and a non-display region; the...
2017/0012057 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE
An array substrate according to an embodiment of the present disclosure may include a base substrate, a gate electrode, a gate insulating layer and an active...
2017/0012056 DISPLAY DEVICE
A display device is disclosed. In one aspect, the display device includes a first wire disposed in the inactive area of the substrate, a first pad overlapping...
2017/0012055 BACKSIDE CONTACT TO A FINAL SUBSTRATE
A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed using a...
2017/0012054 VERTICAL-TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern...
2017/0012053 Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within...
2017/0012052 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, ...
2017/0012051 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The present disclosure provides a method of manufacturing a semiconductor device with a controlled doped concentration of a channel film that is run-through a...
2017/0012050 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a...
2017/0012049 Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing
A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between,...
2017/0012048 SEMICONDUCTOR DEVICE
A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the...
2017/0012047 TRENCH TO TRENCH FIN SHORT MITIGATION
A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage...
2017/0012046 Method and Structure for FinFET Device
The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with...
2017/0012045 SYSTEMS AND METHODS FOR INTEGRATING DIFFERENT CHANNEL MATERIALS INTO A CMOS CIRCUIT BY USING A SEMICONDUCTOR...
A method includes providing a first substrate having first and second regions, fabricating over the first region of the first substrate a channel of a first...
2017/0012044 Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced .sigma.V.sub.T...
2017/0012043 SUBSTRATE CONTACT LAND FOR AN MOS TRANSISTOR IN AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE
A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS...
2017/0012042 METHOD AND STRUCTURE OF FORMING CONTROLLABLE UNMERGED EPITAXIAL MATERIAL
A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set...
2017/0012041 METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS
An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active...
2017/0012040 INTEGRATED DEVICE HAVING MULTIPLE TRANSISTORS
An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the ...
2017/0012039 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a...
2017/0012038 Electrostatic Discharge Protection for Level-Shifter Circuit
In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the...
2017/0012037 Silicon Controlled Rectifier
A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit...
2017/0012036 Electrostatic Discharge Protection Device Comprising a Silicon Controlled Rectifier
An electrostatic discharge protection device including a silicon controlled rectifier. In one example, the silicon controlled rectifier includes a first n-type...
2017/0012035 ELECTROSTATIC DISCHARGE DEVICES AND METHOD OF MAKING THE SAME
In one embodiment, electrostatic discharge (ESD) devices are disclosed.
2017/0012034 SEMICONDUCTOR DEVICE
According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region...
2017/0012033 SEMICONDUCTOR DEVICE AND METHOD FOR FILLING PATTERNS
A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a...
2017/0012032 SEMICONDUCTOR DEVICE
In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween....
2017/0012031 METHODS OF MAKING SEMICONDUCTOR DEVICE PACKAGES AND RELATED SEMICONDUCTOR DEVICE PACKAGES
Methods of making semiconductor device packages may involve providing a fan out wafer including semiconductor-device-package locations. Each ...
2017/0012030 POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT
The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the...
2017/0012029 TSV-CONNECTED BACKSIDE DECOUPLING
An apparatus including a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; and a decoupling...
2017/0012028 RECOVERABLE DEVICE FOR MEMORY BASE PRODUCT
A recoverable device for memory product includes a substrate, a plurality of device dies and at least one local interconnect layer. The device dies are...
2017/0012027 LIGHT EMITTING MODULE
A light emitting module according to an embodiment includes a first insulation film with a light transmissivity, a second insulation film disposed so as to...
2017/0012026 DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME
A display device including a plurality of semiconductor light emitting devices, each corresponding semiconductor light emitting device having a first...
2017/0012025 SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES
A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package...
2017/0012024 Integrated Fan-Out Structure with Openings in Buffer Layer
A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer...
2017/0012023 SOLID-STATE DRIVE
A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively...
2017/0012022 PHOTOSENSITIVE RESIN COMPOSITION, LAMINATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
There are provided a photosensitive resin composition having excellent heat resistance, developability, and curability, a laminate obtained by using a...
2017/0012021 STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING
A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive...
2017/0012020 EMBEDDED DIE-DOWN PACKAGE-ON-PACKAGE DEVICE
An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of...
2017/0012019 SOLDER BUMP STRETCHING METHOD FOR FORMING A SOLDER BUMP JOINT IN A DEVICE
A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder...
2017/0012018 LEAD-FREE SOLDERING METHOD AND SOLDERED ARTICLE
In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is...
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