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Patent # Description
2017/0011017 CONTENT BROWSER SYSTEM USING MULTIPLE LAYERS OF GRAPHICS COMMANDS
Server systems are disclosed that receive content requests and respond with hardware-independent graphics commands instead of, or in addition to, unprocessed...
2017/0011016 AUTOMATED DOCUMENT GENERATION WITH XQML
Embodiments are directed to a markup language that allows content and logic statements to be used in the same syntax, as well as generating a markup language...
2017/0011015 CONTENT EXTRACTION SYSTEM
A system includes a content extraction engine comprising at least one processor and configured to receive a content page including first product data for a...
2017/0011014 SHARING USAGE OF RESOURCES WITH INTERESTED USERS
While interacting with resources such as databases and data sets, a user of an organization may create a usage of a resource that is interesting or has value....
2017/0011013 ELECTRONIC FILE STRUCTURE, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, ELECTRONIC FILE GENERATION...
Herein disclosed is an electronic file structure configured to include a setting region having a name of an anchor indicative of a predetermined location, and...
2017/0011012 AUTOMATIC VERIFICATION OF GRAPHIC RENDITION OF JSON DATA
Aspects provide automatic verification of graphic rendition of JavaScript Object Notation (JSON) data by using a baseline JSON file to render data values of a...
2017/0011011 RULE-BASED LAYOUT OF CHANGING INFORMATION
Displaying application output in a manner that is not predetermined by the application, nor by the display. The computing system associated with the display...
2017/0011010 METHOD FOR DISPLAYING WEB CONTENT AND ELECTRONIC DEVICE SUPPORTING THE SAME
A system and method are provided for displaying a web content, which enables a web content to be conveniently used on multiple screens and provide interactions...
2017/0011009 ELECTRONIC DEVICE AND METHOD FOR PROVIDING INFORMATION ASSOCIATED WITH NEWS CONTENT
An electronic device includes: a tuner configured to receive news content; and a controller configured to extract text information from the news content, map...
2017/0011008 Anomaly Detection Method, Program, and System
A method providing an analytical technique introducing label information into an anomaly detection model. Effective utilization of label information is based...
2017/0011007 LAND BATTLE PROCESS EVALUATION METHOD AND SYSTEM THEREOF
A land battle process evaluation method and system thereof are provided. The land battle result evaluation method includes a flow network for presenting the...
2017/0011006 DEVICE AND METHOD TO PROCESS DATA IN PARALLEL
A method and apparatus for processing data are provided. The processor includes an input buffer, a data extractor, a multiplier, and an adder. The input buffer...
2017/0011005 Method and Apparatus for Decimation in Frequency FFT Butterfly
A pipelined decimation in frequency FFT butterfly method, and an apparatus to perform this method comprising: a data memory with at least one read port and one...
2017/0011004 Method and Apparatus for Generating Harmonics Using Polynomial Non-Linear Functions
A method and apparatus for generating harmonics using polynomial non-linear functions. Polynomial functions are used to produce harmonics of an input signal up...
2017/0011003 Efficient Means of Combining Network Traffic for 64Bit and 31Bit Workloads
A method, system and computer-usable medium are disclosed for performing a network traffic combination operation. With the network traffic combination...
2017/0011002 PERIPHERAL COMPONENT INTERCONNECT EXPRESS CARD
A peripheral component interconnect express (PCIe) card may include a base card, a mezzanine card and mezz connectors. The base card may be coupled to a host...
2017/0011001 USB CONTROL CIRCUIT WITH BUILT-IN SIGNAL REPEATER CIRCUIT
A USB control circuit of a USB hub device includes: an upstream MAC-layer circuit; a downstream MAC-layer circuit; a first USB PHY-layer circuit; a second USB...
2017/0011000 Subscriber Station for a Bus System, and Method for Increasing the Data Rate of a Bus System
The disclosure relates to a participant station for a bus system and to a method for increasing the data rate of a bus system. The participant station...
2017/0010999 ADJUSTING AN OPTIMIZATION PARAMETER TO CUSTOMIZE A SIGNAL EYE FOR A TARGET CHIP ON A SHARED BUS
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for...
2017/0010998 COMMUNICATION APPARATUS, COMMUNICATION METHOD, AND COMPUTER READABLE MEDIUM
A gateway apparatus (103) receives a request frame transmitted from a system controller (101) to an indoor unit 1 (111), and determines whether a sensor...
2017/0010997 USB CONTROL CIRCUIT WITH BUILT-IN BYPASS FUNCTION
A USB hub device includes an upstream port and a downstream port. A USB control circuit of the USB control circuit includes an upstream interface; a downstream...
2017/0010996 SYSTEM FOR EXPANSION OF INPUT/OUTPUT PORTS OF A COMPUTER
A computer I/O port system includes a CPU, a plurality of switches and a plurality of I/O ports connecting with each other by PCI Express buses. A first switch...
2017/0010995 Sideband Serial Channel for PCI Express Peripheral Devices
Obtaining data about a peripheral device deployed in a computing environment. A method includes transmitting a primary data stream across a shared...
2017/0010994 Universal Input/Output Circuit
A universal input/output circuit for building automation is provided that may avoid issues related to capacitor soakage, thereby giving more accurate...
2017/0010993 COMPUTING SYSTEM CONTROL
In one example in accordance with the present disclosure, a computing system is provided. The computing system includes a first bus controller to control X bus...
2017/0010992 POWER SAVING FEATURE FOR STORAGE SUBSYSTEMS
Disclosed herein is a technique for maintaining a responsive user interface for a user while preserving battery life of a user device by dynamically...
2017/0010991 Providing State Storage in a Processor for System Management Mode
In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state...
2017/0010990 EMBEDDED STORAGE DEVICE
An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave...
2017/0010989 MEMORY SYSTEM
A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of...
2017/0010988 ACTIVATION METHOD OF A UNIVERSAL SERIAL BUS COMPATIBLE FLASH DEVICE AND RELATED UNIVERSAL SERIAL BUS COMPATIBLE...
An activation method of a universal serial bus (USB) compatible flash device is disclosed, wherein the USB compatible flash device includes a controller and a...
2017/0010987 ADJUSTING AN OPTIMIZATION PARAMETER TO CUSTOMIZE A SIGNAL EYE FOR A TARGET CHIP ON A SHARED BUS
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for...
2017/0010986 Adaptive Resource Management in a Pipelined Arbiter
A resource arbiter in a system with multiple shared resources and multiple requestors may implement an adaptive resource management approach that takes...
2017/0010985 ADJUSTING AN OPTIMIZATION PARAMETER TO CUSTOMIZE A SIGNAL EYE FOR A TARGET CHIP ON A SHARED BUS
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for...
2017/0010984 ADJUSTING AN OPTIMIZATION PARAMETER TO CUSTOMIZE A SIGNAL EYE FOR A TARGET CHIP ON A SHARED BUS
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for...
2017/0010983 INPUT DEVICE IDENTIFYING COMPUTER SYSTEM AND IDENTIFICATION METHOD THEREOF
An input device identifying a computer system includes: a memory, for storing a configuration descriptor, an interface descriptor, a human interface device...
2017/0010982 SECURE HANDLING OF MEMORY CACHES AND CACHED SOFTWARE MODULE IDENTITIES FOR A METHOD TO ISOLATE SOFTWARE MODULES...
In an aspect, a cache memory device receives a request to read an instruction or data associated with a memory device. The request includes a first realm...
2017/0010981 MEMORY CIRCUIT USING RESISTIVE RANDOM ACCESS MEMORY ARRAYS IN A SECURE ELEMENT
A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories...
2017/0010980 METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING ADDRESS DATA
A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device,...
2017/0010979 MANAGEMENT OF MEMORY PAGES
In a method for managing memory pages, responsive to determining that a server is experiencing memory pressure, one or more processors identifying a first...
2017/0010978 FORK-SAFE MEMORY ALLOCATION FROM MEMORY-MAPPED FILES WITH ANONYMOUS MEMORY BEHAVIOR
Methods and systems are provided for fork-safe memory allocation from memory-mapped files. A child process may be provided a memory mapping at a same virtual...
2017/0010977 SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER
Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one...
2017/0010976 TRANSLATION LOOKASIDE BUFFER PERFORMANCE BY EXPLOITING SPACIAL LOCALITY
A system may include a memory that includes a plurality of pages, a processor, and a translation lookaside buffer (TLB) that includes a plurality of entries....
2017/0010975 NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES
A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are...
2017/0010974 ADDRESS RANGE PRIORITY MECHANISM
Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a...
2017/0010973 PROCESSOR WITH EFFICIENT PROCESSING OF LOAD-STORE INSTRUCTION PAIRS
A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions...
2017/0010972 PROCESSOR WITH EFFICIENT PROCESSING OF RECURRING LOAD INSTRUCTIONS
A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions...
2017/0010971 PROCESSOR WITH EFFICIENT PROCESSING OF RECURRING LOAD INSTRUCTIONS FROM NEARBY MEMORY ADDRESSES
A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions...
2017/0010970 FACILITATING PREFETCHING FOR DATA STREAMS WITH MULTIPLE STRIDES
The disclosed embodiments relate to a system that generates prefetches for a stream of data accesses with multiple strides. During operation, while a processor...
2017/0010969 COMPUTING DEVICE AND METHOD FOR PROCESSING DATA IN CACHE MEMORY OF THE COMPUTING DEVICE
In a method for processing cache data of a computing device, a storage space of the storage device is divided into sections, and a section number of each data...
2017/0010968 SYSTEM AND METHOD FOR DATA CACHING IN PROCESSING NODES OF A MASSIVELY PARALLEL PROCESSING (MPP) DATABASE SYSTEM
The present technology relates to managing data caching in processing nodes of a massively parallel processing (MPP) database system. A directory is maintained...
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