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Patent # Description
2017/0018522 FLIP CHIP BONDING ALLOYS
A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising...
2017/0018521 Protrusion Bump Pads for Bond-on-Trace Processing
An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion...
2017/0018520 USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE
A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation...
2017/0018519 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump...
2017/0018518 METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL
A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow...
2017/0018517 MICROELECTRONIC ASSEMBLIES FORMED USING METAL SILICIDE, AND METHODS OF FABRICATION
Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal,...
2017/0018516 SELF-ALIGNED UNDER BUMP METAL
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer,...
2017/0018515 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS, AND WAFER LIFT PIN-HOLE...
To shorten a maintenance time of a semiconductor manufacturing apparatus and to improve productivity of a semiconductor manufacturing line. A semiconductor...
2017/0018514 TRANSMISSION LINE FOR 3D INTEGRATED CIRCUIT
A semiconductor transmission line substructure and methods of transmitting RF signals are described. The semiconductor transmission line substructure can...
2017/0018513 SEMICONDUCTOR PACKAGE INCLUDING AN ANTENNA FORMED IN A GROOVE WITHIN A SEALING ELEMENT
There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package...
2017/0018512 SEMICONDUCTOR DEVICE
The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of...
2017/0018511 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM
A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically...
2017/0018510 MICROELECTRONIC ASSEMBLIES WITH CAVITIES, AND METHODS OF FABRICATION
Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the...
2017/0018509 THROUGH-BODY VIA LINER DEPOSITION
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an...
2017/0018508 SUPPORT FOR LONG CHANNEL LENGTH NANOWIRE TRANSISTORS
A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire...
2017/0018507 Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die
A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited...
2017/0018506 TUNGSTEN ALLOYS IN SEMICONDUCTOR DEVICES
Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for...
2017/0018505 WIRING BOARD WITH EMBEDDED COMPONENT AND INTEGRATED STIFFENER AND METHOD OF MAKING THE SAME
A wiring board with embedded component and integrated stiffener is characterized in that an embedded semiconductor device, a first routing circuitry, an...
2017/0018504 SEMICONDUCTOR DEVICE HAVING STRUCTURE FOR IMPROVING VOLTAGE DROP AND DEVICE INCLUDING THE SAME
A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers...
2017/0018503 SEMICONDUCTOR DIE WITH A METAL VIA
A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor,...
2017/0018502 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time,...
2017/0018501 VIA STRUCTURES FOR THERMAL DISSIPATION
An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in...
2017/0018500 STRUCTURE WITH CONDUCTIVE PLUG AND METOD OF FORMING THE SAME
Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive...
2017/0018499 NECKED INTERCONNECT FUSE STRUCTURE FOR INTEGRATED CIRCUITS
Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied...
2017/0018498 Method Of Semiconductor Integrated Circuit Fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is...
2017/0018497 SOC WITH INTEGRATED VOLTAGE REGULATOR USING PREFORMED MIM CAPACITOR WAFER
In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit...
2017/0018496 Interconnect Structure for Semiconductor Devices
An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a...
2017/0018495 SEMICONDUCTOR DEVICE FOR ELECTRIC POWER
Herein provided are: a ceramic board; a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of...
2017/0018494 INTERPOSER AND CIRCUIT SUBSTRATE
An interposer includes an insulating plate including insulating layers and having first, second, third and fourth surfaces such that the second surface is on...
2017/0018493 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a...
2017/0018492 INTERPOSERS, SEMICONDUCTOR DEVICES, METHOD FOR MANUFACTURING INTERPOSERS, AND METHOD FOR MANUFACTURING...
An interposer which can better prevent detachment of a conductive layer pattern due to thermal expansion and thermal contraction. The interposer includes a...
2017/0018491 Substrate Structure and Manufacturing Method Thereof
A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a dielectric material layer, a first conductive wiring...
2017/0018490 VIA STRUCTURE AND CIRCUIT BOARD HAVING THE VIA STRUCTURE
The present disclosure provides a via structure and a multilayer circuit board including the via structure. The via structure is provided in three or more...
2017/0018489 SOLDER BOND SITE INCLUDING AN OPENING WITH DISCONTINOUS PROFILE
Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least...
2017/0018488 INTEGRATED POWER MODULE AND MANUFACTURING METHOD THEREOF
An integrated power module comprising a power board including at least one power switching device, a driver board including at least one driver for driving a...
2017/0018487 THERMAL ENHANCEMENT FOR QUAD FLAT NO LEAD (QFN) PACKAGES
Integrated circuit packages with enhanced thermal characteristics are provided. For example, in embodiments, a QFN (quad flat no lead) package includes a die...
2017/0018486 SEMICONDUCTOR MODULE
A semiconductor module can be realized, which is formed by mounting an electronic component and a bus bar by solder on a lead frame including a plurality of...
2017/0018485 FLIPPED DIE STACK ASSEMBLIES WITH LEADFRAME INTERCONNECTS
A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of...
2017/0018484 SEMICONDUCTOR DEVICE
The semiconductor device includes a semiconductor element, and an electro-conductive first plate-like part electrically connected to a top-face-side electrode...
2017/0018483 INTEGRATED CIRCUIT CHIP FABRICATION LEADFRAME
One example includes a conductive leadframe configured to couple to an integrated circuit (IC) chip die on a contact surface of the IC chip die. The conductive...
2017/0018482 RECESSED LEAD LEADFRAME PACKAGES
Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads...
2017/0018481 COMPRESSIBLE THERMAL INTERFACE MATERIALS
Provided is a compressible thermal interface material including a polymer, a thermally conductive filler, and a phase change material. A formulation for...
2017/0018480 SEMICONDUCTOR DEVICE
A control terminal 14 of a semiconductor device has a recessed portion 14c. A resin case 15 is provided with a fixing member 152 engaging with and fixing a...
2017/0018478 VIA STRUCTURES FOR THERMAL DISSIPATION
An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in...
2017/0018477 METHOD FOR PROTECTING LAYER BY FORMING HYDROCARBON-BASED EXTREMELY THIN FILM
A method for protecting a layer includes: providing a substrate having a target layer and forming a protective layer on the target layer, said protective layer...
2017/0018476 Die Packages and Methods of Manufacture Thereof
Die packages and method of manufacturing the same are disclosed. In an embodiment, a method of manufacturing a die package may include forming an encapsulated...
2017/0018475 SEMICONDUCTOR DEVICE AND METHOD
Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die...
2017/0018474 ELECTRONIC COMPONENT PACKAGE
An electronic component package includes: a core including a cavity, a first resin layer, a second resin layer and a reinforcing layer disposed between the...
2017/0018473 PHOSPHONIUM COMPOUND, EPOXY RESIN COMPOSITION INCLUDING THE SAME AND SEMICONDUCTOR DEVICE PREPARED USING THE SAME
A phosphonium compound, an epoxy resin composition including the same, a semiconductor device encapsulated with the same, and a method of encapsulating a...
2017/0018472 Underfill Material, Laminated Sheet and Method for Producing Semiconductor Device
An underfill material having sufficient curing reactivity, and capable of achieving a small change in viscosity and good electrical connection even when loaded...
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