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Patent # Description
2017/0017594 Stacked Semiconductor Device Assembly in Computer System
This application is directed to a stacked semiconductor device assembly including first and second integrated circuit (IC) devices. Each of the first and...
2017/0017593 PROACTIVE QUALITY OF SERVICE IN MULTI-MATRIX SYSTEM BUS
A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a...
2017/0017592 TRANSMISSION TERMINAL, NON-TRANSITORY RECORDING MEDIUM, TRANSMISSION METHOD, AND TRANSMISSION SYSTEM
A transmission terminal includes at least one processor configured to transmit a terminal information request to request the number of transmission terminals...
2017/0017591 DATA PROCESSING SYSTEM
A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data...
2017/0017590 MEMORY SYSTEM ARCHITECTURE INCLUDING SEMI-NETWORK TOPOLOGY WITH SHARED OUTPUT CHANNELS
A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each...
2017/0017589 AGGREGATION OF INTERRUPTS USING EVENT QUEUES
Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an...
2017/0017588 STORAGE REGION MAPPING FOR A DATA STORAGE DEVICE
A data storage device includes a controller coupled to multiple groups of data storage dies, such as a meta-meta-die. The controller is configured to write...
2017/0017587 LOW-POWER CLOCKING FOR A HIGH-SPEED MEMORY INTERFACE
Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a...
2017/0017586 MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS
A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host...
2017/0017585 Fabric Independent PCIE Cluster Manager
A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster...
2017/0017584 SPI Interface With Less-Than-8-Bit Bytes And Variable Packet Size
A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial...
2017/0017583 TRANSACTIONAL MEMORY SUPPORT
An asymmetric multiprocessor system (2) includes a plurality of processor cores (4, 6) supporting transactional memory via controllers (14, 16) as well as one...
2017/0017582 DATA STORAGE APPARATUS, CODING UNIT, SYSTEMS INCLUDING THE SAME, METHOD OF CODING AND METHOD OF READING DATA
In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one...
2017/0017581 Communication Efficient Secret Sharing
Methods for distributed storage in accordance with embodiments of the invention enable secret sharing. One embodiment includes encoding source data using an...
2017/0017580 METHOD AND APPARATUS FOR IMPLEMENTING A HETEROGENEOUS MEMORY SUBSYSTEM
An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping...
2017/0017579 FLEXIBLE I/O DMA ADDRESS ALLOCATION IN VIRTUALIZED SYSTEMS
A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to...
2017/0017578 GENERATION OF RANDOM ADDRESS MAPPING IN NON-VOLATILE MEMORIES USING LOCAL AND GLOBAL INTERLEAVING
Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for...
2017/0017577 INVALIDATING A RANGE OF TWO OR MORE TRANSLATION TABLE ENTRIES AND INSTRUCTION THEREFOR
An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be...
2017/0017576 Self-adaptive Cache Architecture Based on Run-time Hardware Counters and Offline Profiling of Applications
Aspects include computing devices, systems, and methods for implementing generating a cache memory configuration. A server may apply machine learning to...
2017/0017575 Apparatus and Method of Performing Agentless Remote IO Caching Analysis, Prediction, Automation, and...
A host device includes a controller configured to receive input/output (TO) access information associated with an IO workload, the IO access information...
2017/0017574 EFFICIENT CACHE WARM UP BASED ON USER REQUESTS
One embodiment of the present invention provides a system for efficiently warming up a cache. During operation, the system determines a cache prediction based...
2017/0017573 DATA ACCESS CONTROL APPARATUS
A data access control apparatus of an embodiment includes an update region management apparatus including an update region management unit configured to...
2017/0017572 Compensating for Aging in Integrated Circuits
An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of...
2017/0017571 METHOD AND APPARATUS FORI N-LINE DEDUPLICATION IN STORAGE DEVICES
A storage device for deduplicating data includes a memory that stores machine instructions and a controller coupled to the memory to execute the machine...
2017/0017570 MAPPING TABLE UPDATING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
A mapping table updating method for a rewritable non-volatile memory module is provided. The method includes: allocating a mapping table storage area for...
2017/0017569 RESOURCE MANAGEMENT IN MAPREDUCE ARCHITECTURE AND ARCHITECTURAL SYSTEM
Resource management in MapReduce architecture and architectural system. The present invention provides an apparatus for resource management in the MapReduce...
2017/0017568 System And Method For Implementing Distributed-Linked Lists For Network Devices
A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory...
2017/0017567 System And Method For Implementing Distributed-Linked Lists For Network Devices
A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory...
2017/0017566 MODULAR PLUG-AND-PLAY SYSTEM FOR CONTINUOUS MODEL DRIVEN TESTING
A method for testing an application running on an electronic device includes parsing, by a test processor, a state model of the application representing...
2017/0017564 PREDICTIVE APPROACH TO ENVIRONMENT PROVISIONING
Embodiments of the present invention provide methods, systems, and computer program products for building an environment. Embodiments of the present invention...
2017/0017563 DETECTING RACE CONDITION VULNERABILITIES IN COMPUTER SOFTWARE APPLICATIONS
Testing computer software applications is performed by identifying first and second executable portions of the computer software application, where the...
2017/0017562 PERFORMANCE OF A WRAPPED APPLICATION
Systems, methods, and computer-readable media for securing a mobile device application using an application wrapper while preserving and/or improving...
2017/0017561 SOFTWARE DETECTION METHOD AND DEVICE
Provided are a software detection method and device. The method comprises: matching software information about software to be detected with information in one...
2017/0017560 MONITOR CONTROL SYSTEM AND DATA COLLECTION APPARATUS
A data collection apparatus includes a data collection section configured to receive sequential time-series output data pieces for each of data sources, a data...
2017/0017559 SYSTEM AND METHOD OF MONITORING A SERIAL BUS
A system and method are provided for managing internal-computer system communications in an SPI management system. The system includes a storage device, at...
2017/0017558 NON-INTRUSIVE PROBE FOR DOUBLE DATA RATE INTERFACE
A method and apparatus using a non-intrusive probe for testing double data rate interfaces is provided. The method begins with the generation of at least one...
2017/0017557 STORAGE CONTROLLING DEVICE, STORAGE CONTROLLING METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM
A storage controlling device including a memory and a processor configured to obtain information on each of a plurality of remaining lives of each of a...
2017/0017556 METHODS FOR RECONFIGURING A STORAGE CONTROLLER WHEN CONTROL LOGIC FAILS AND APPARATUSES USING THE SAME
A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a...
2017/0017555 MEMORY SYSTEM
According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory, a second memory, and a controller. The first...
2017/0017554 METHODS AND SYSTEMS FOR REMOVING VIRTUAL MACHINE SNAPSHOTS
Techniques are described herein which minimize the impact of virtual machine snapshots on the performance virtual machines and hypervisors. In the context of a...
2017/0017553 System and Method For Mainframe Computers Backup and Restore
A computer-implemented method, system and computer program product, the method comprising: receiving a request for backing up data from a mainframe on a backup...
2017/0017552 INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS
An update information managing unit, when specific data is updated, adds update information to the specific data, prevents a predetermined program from...
2017/0017551 COORDINATING FILE SYNCHRONIZATION BETWEEN A SYNC ENGINE AND ANOTHER APPLICATION THAT SUPPORTS DOCUMENT...
A synchronization engine detects a notification of a change to a file. It determines whether an application associated with the file has indicated that the...
2017/0017550 STORAGE SYSTEM
A storage system according to the present invention comprises a controller and multiple storage devices, constitutes a RAID group from (n+m) number of storage...
2017/0017549 NODE, ARITHMETIC PROCESSING DEVICE, AND ARITHMETIC PROCESSING METHOD
A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to...
2017/0017548 Systems and Methods for Retaining Non-Converged Data Sets for Additional Processing
Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multiple codeword processing in a data...
2017/0017547 PROTECTING DATA INTEGRITY IN DE-DUPLICATED STORAGE ENVIRONMENTS IN COMBINATION WITH SOFTWARE DEFINED NATIVE RAID
A mechanism is provided in a data processing system for securing data integrity in de-duplicated storage environments in combination with software defined...
2017/0017546 Dynamic Enabling of Redundant Memory Cells During Operating Life
A memory, such as a non-volatile ferroelectric memory, including both error correction coding (ECC) capability and redundant memory cells. During the system...
2017/0017545 ERROR CORRECTION DEVICE, SEMICONDUCTOR STORAGE DEVICE, AND ERROR CORRECTION METHOD
There is provided an error correction device with a simple configuration and a high correction capability. An error correction device which can perform c...
2017/0017544 SYSTEMS AND METHODS FOR PROVIDING LOW LATENCY READ PATH FOR NON-VOLATILE MEMORY
Aspects of the disclosure relate to storage systems for providing low latency read access of a non-volatile memory. One such system includes a non-volatile...
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