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Patent # Description
2017/0084757 SCALABLE VOLTAGE SOURCE
A scalable voltage source having a number N of partial voltage sources implemented as semiconductor diodes connected to one another in series, wherein each of...
2017/0084749 VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IMPLANT
Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate...
2017/0084741 ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES
A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The...
2017/0084740 3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and...
2017/0084733 SELF-ALIGNED SIGE FINFET
A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the...
2017/0084732 III-V FIN ON INSULATOR
A method of forming a semiconductor structure in which a III-V compound semiconductor channel fin portion is formed on a dielectric material is provided. The...
2017/0084727 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device including a mesa portion formed on a front surface side of a semiconductor substrate; a floating portion formed on the front surface...
2017/0084722 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an...
2017/0084717 Source/Drain Regions for High Electron Mobility Transistors (HEMT) and Methods of Forming Same
An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the...
2017/0084699 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has...
2017/0084685 SEMICONDUCTOR DEVICE
A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well...
2017/0084676 Organic Light Emitting Display Device
An organic light emitting display device includes an overcoating layer on a substrate; a first electrode on the overcoating layer; a bank layer on the...
2017/0084665 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing an image sensor device includes, in a first manufacturing facility, forming a first set of patterned silicon, metal, and insulating...
2017/0084664 METHOD OF FORMING POLYSILICON GATE STRUCTURE IN IMAGE SENSOR DEVICE
A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a...
2017/0084663 OPTOELECTRONIC MODULES THAT HAVE SHIELDING TO REDUCE LIGHT LEAKAGE OR STRAY LIGHT, AND FABRICATION METHODS FOR...
Various optoelectronic modules are described that include an optoelectronic device (e.g., a light emitting or light detecting element) and a transparent cover....
2017/0084662 OPTICAL RECEIVER MODULE AND METHOD OF MAKING OPTICAL RECEIVER MODULE
An optical receiver module includes a substrate, photodetectors mounted on a first surface of the substrate, amplifiers mounted on the first surface of the...
2017/0084644 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
Disclosed is a thin film transistor array panel including: a substrate; a gate line provided on the substrate and extending in a first direction; a data line...
2017/0084642 ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE
An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first...
2017/0084641 ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE
An array substrate includes a substrate, and a first TFT and a second TFT on the substrate. The second TFT is a low-temperature poly silicon TFT. The first TFT...
2017/0084640 Array Substrate and Manufacturing Method Thereof, and Display Apparatus Thereof
An embodiment of the present disclosure provides an array substrate and a manufacturing method thereof and a display apparatus. The array substrate includes a...
2017/0084629 SEMICONDUCTOR DEVICE WITH REDUCED POLY SPACING EFFECT
A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate with a semiconductor layer, forming a first gate...
2017/0084602 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD FOR PRODUCING AN ELECTROSTATIC DISCHARGE PROTECTION DEVICE
An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The...
2017/0084592 Method for Fabricating a Semiconductor Integrated Chip
The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection...
2017/0084591 LOCALIZED REDISTRIBUTION LAYER STRUCTURE FOR EMBEDDED COMPONENT PACKAGE AND METHOD
An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active...
2017/0084583 SEMICONDUCTOR PACKAGE ASSEMBLIES WITH SYSTEM-ON-CHIP (SOC) PACKAGES
A semiconductor package assembly includes a first semiconductor package. The first semiconductor package has a semiconductor die having pads thereon, first...
2017/0084578 FLEXIBLY-WRAPPED INTEGRATED CIRCUIT DIE
Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are...
2017/0084573 MICROELECTRONIC PACKAGE DEBUG ACCESS PORTS
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,...
2017/0084568 SEMICONDUCTOR MODULE
In the semiconductor module according to the present invention, a conducting member which is used to electrically connect a semiconductor element arranged on a...
2017/0084566 METHOD OF MANUFACTURING ELECTRONIC COMPONENT MODULE AND ELECTRONIC COMPONENT MODULE
A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each...
2017/0084562 PACKAGE STRUCTURE, CHIP STRUCTURE AND FABRICATION METHOD THEREOF
A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on...
2017/0084551 Transient Electronic Device With ION-Exchanged Glass Treated Interposer
A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger...
2017/0084541 SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE USING THE SAME AND MANUFACTURING METHOD THEREOF
A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive...
2017/0084534 ELECTRICALLY CONDUCTIVE INTERCONNECT INCLUDING VIA HAVING INCREASED CONTACT SURFACE AREA
An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second...
2017/0084525 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect...
2017/0084522 SEMICONDUCTOR DEVICE AND METERING APPARATUS
A semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that...
2017/0084513 SEMICONDUCTOR PACKAGE
A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided....
2017/0084504 METHODS OF MANUFACTURING LIGHT SOURCE MODULE
Manufacturing a light source module may include mounting light emitting devices on substrates on an upper surface of a carrier, mounting optical devices to...
2017/0084499 Structure and Formation Method of Semiconductor Device Structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a...
2017/0084495 Guard Rings including Semiconductor Fins and Regrown Regions
A method includes forming a gate stack over a semiconductor fin, wherein the semiconductor fin forms a ring, and etching a portion of the semiconductor fin not...
2017/0084487 SEAM HEALING OF METAL INTERCONNECTS
Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment,...
2017/0084484 SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD THEREFOR
A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least...
2017/0084473 Systems and Methods for Controlling an Etch Process
A system for controlling an etch process includes and etching tool, a metrology tool, and a controller. The etching tool is controllable via a set of control...
2017/0084457 POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a polycrystalline silicon thin film transistor device includes the following steps. A substrate is provided, and a buffer layer having...
2017/0084450 SEMICONDUCTOR DEVICE STRUCTURES COMPRISING POLYCRYSTALLINE CVD DIAMOND WITH IMPROVED NEAR-SUBSTRATE THERMAL...
Disclosed is a semiconductor device structure including a III-V compound semiconductor material layer, a polycrystalline CVD diamond material layer, and an...
2017/0084409 CLUTCH MECHANISM FOR ENERGY STORAGE DEVICE IN GAS INSULATED CIRCUIT BREAKER AND GAS INSULATED CIRCUIT BREAKER...
A clutch mechanism includes a transmission shaft, driven by an output shaft of a motive power device; a clutch element, including an engagement end, in...
2017/0084402 LOW RESISTANCE ULTRACAPACITOR ELECTRODE AND MANUFACTURING METHOD THEREOF
A carbon-based electrode includes activated carbon, carbon black, and a binder. The binder is fluoropolymer having a molecular weight of at least 500,000 and a...
2017/0084395 CAPACITOR STRUCTURE WITH ACOUSTIC NOISE SELF-CANCELING CHARACTERISTICS
This application relates to capacitors that resist deformation because of the configuration of their conductive and dielectric layers. The capacitors are...
2017/0084394 Polyetherimide Compatible Polymer Blends for Capacitor Films
A uniaxially-stretched, high yield extruded capacitor film comprising a compatible polymer blend comprising a polyetherimide and a polyphenylene ether sulfone,...
2017/0084393 Polyetherimide Miscible Polymer Blends for Capacitor Films
A uniaxially-stretched, high yield extruded capacitor film comprising a miscible polymer blend comprising a polyetherimide and a poly(carbonate-arylate ester),...
2017/0084386 DC COMPENSATION FOR HIGH DC CURRENT IN TRANSFORMER
A system for compensating one or more DC components in an electrical system includes one or more sensors for sensing the one or more DC components. The system...
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