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Patent # Description
2017/0098653 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
Methods of manufacturing a semiconductor device are provided. Methods may include forming first to third regions having densities different from one another on...
2017/0098652 SEMICONDUCTOR DEVICE HAVING CAPACITOR AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE
A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not...
2017/0098651 Offset-Printing Method for Three-Dimensional Package
The present invention discloses an offset-printing method for a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package. The...
2017/0098650 Offset-Printing Method for Three-Dimensional Printed Memory with Multiple Bits-Per-Cell
The present invention discloses an offset-printing method for a three-dimensional printed memory with multiple bits-per-cell. The mask-patterns for different...
2017/0098649 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including...
2017/0098648 INTEGRATED CIRCUIT HAVING FIELD-EFFECT TRASISTORS WITH DIELECTRIC FIN SIDEWALL STRUCTURES AND MANUFACTURING...
An integrated circuit includes a first semiconductor fin, a first epitaxy structure, and at least two first dielectric fin sidewall structures. The first...
2017/0098647 SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR LAYER, UNIT CELLS,...
A semiconductor device includes a first silicon carbide semiconductor layer, a source including a source pad and a source wiring, a gate including a gate pad...
2017/0098646 ESD DEVICE COMPATIBLE WITH BULK BIAS CAPABILITY
A device having an electrostatic discharge structure includes a bulk substrate having a first dopant conductivity, first wells formed adjacent to a surface of...
2017/0098645 SCRS with Checker Board Layouts
An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of...
2017/0098644 ESD PROTECTION DEVICE
An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type....
2017/0098643 HIGH VOLTAGE BIPOLAR STRUCTURE FOR IMPROVED PULSE WIDTH SCALABILITY
According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor...
2017/0098642 LED MODULE AND METHOD OF MANUFACTURING THE SAME
A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead,...
2017/0098641 SEMICONDUCTOR DEVICE HAVING JUMPER PATTERN
According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side...
2017/0098640 Semiconductor Structure and Manufacturing Method Thereof
A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die...
2017/0098639 DIE STACKING METHOD
A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to...
2017/0098638 DEVICE FOR CONNECTING AT LEAST ONE NANO-OBJECT ASSOCIATED WITH A CHIP ENABLING A CONNECTION TO AT LEAST ONE...
Production of a device for connecting a nano-object to an external electrical system (SEE) including: a first chip provided with conducting areas (8a, 8b)...
2017/0098637 CIRCUIT MODULE AND METHOD FOR MANUFACTURING THE SAME
A module board includes insulating layers, ground electrodes, signal electrodes, and interlayer vias. Electronic components are mounted on a front surface of...
2017/0098636 LIGHT EMITTING DEVICE
A light emitting device includes a package having a recess which includes a bottom surface. A first bottom surface of a first light emitting element is put on...
2017/0098635 OPTOCOUPLER WITH INDICATION OF LIGHT SOURCE POWER SUPPLY FAILURE
An optical system, an optocoupler, and an isolation device are provided. The disclosed optical system includes at least one photodetector that receives light...
2017/0098634 INTEGRATED DEVICE COMPRISING EMBEDDED PACKAGE ON PACKAGE (PoP) DEVICE
An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package...
2017/0098633 PACKAGE-ON-PACKAGE (PoP) DEVICE COMPRISING A GAP CONTROLLER BETWEEN INTEGRATED CIRCUIT (IC) PACKAGES
A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located...
2017/0098632 Three-Dimensional 3D-oP-Based Package
The present invention discloses a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D.sup.2-oP). The mask-patterns for...
2017/0098631 ELECTRONIC COMPONENT, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING ELECTRONIC APPARATUS
An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second...
2017/0098630 Semiconductor Chips Including Redistribution Interconnections and Related Methods and Semiconductor Packages
A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating...
2017/0098629 STACKED FAN-OUT PACKAGE STRUCTURE
A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A...
2017/0098628 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the...
2017/0098627 INTERCONNECT STRUCTURES FOR FINE PITCH ASSEMBLY OF SEMICONDUCTOR STRUCTURES
A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first...
2017/0098626 BATTERY PROTECTION PACKAGE AND PROCESS OF MAKING THE SAME
The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery...
2017/0098625 SEMICONDUCTOR DEVICE
A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate...
2017/0098624 SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS
A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip,...
2017/0098623 IC STRUCTURE WITH ANGLED INTERCONNECT ELEMENTS
Aspects of the present disclosure include integrated circuit (IC) structures with angled interconnect elements. An IC structure according to the present...
2017/0098622 SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
A semiconductor device, a semiconductor package including the same, and a method of fabricating the same are disclosed. The method may include providing an...
2017/0098621 ELECTRICAL BARRIER LAYERS
An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron,...
2017/0098620 Semiconductor Device Load Terminal
A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and...
2017/0098619 SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same are provided. The semiconductor chip includes an...
2017/0098618 SEMICONDUCTOR DEVICE ATTACHED TO AN EXPOSED PAD
The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an...
2017/0098617 Chip-on-Substrate Packaging on Carrier
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a...
2017/0098616 WAFER REINFORCEMENT TO REDUCE WAFER CURVATURE
A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor...
2017/0098615 PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT
A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion...
2017/0098614 Contacts for Semiconductor Devices and Methods of Forming Thereof
A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with...
2017/0098613 INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME
A semiconductor device includes a semiconductor substrate, an epitaxy structure present in the semiconductor substrate, and a silicide present on a textured...
2017/0098612 Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge...
A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A...
2017/0098611 METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT AND AN ELECTRONIC COMPONENT
A method for manufacturing an electronic component can include the following steps: providing a semiconductor arrangement comprising a carrier structure which...
2017/0098610 Semiconductor Device and Method of Using Substrate Having Base and Conductive Posts to Form Vertical...
A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel,...
2017/0098609 Source-Gate Region Architecture in a Vertical Power Semiconductor Device
A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked...
2017/0098608 SEMICONDUCTOR DEVICE HAVING A POWER RAIL
A semiconductor device is provided as follows. An active region extends along a first direction. A gate line overlaps the active region and extending along a...
2017/0098607 Configurable Routing for Packaging Applications
Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die...
2017/0098606 SEMICONDUCTOR STRUCTURE WITH ULTRA THICK METAL AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer...
2017/0098605 INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF
An interconnection structure includes a first dielectric layer, at least one first conductor, and an etch stop layer. The first conductor is disposed partially...
2017/0098604 ISOLATION DEVICE
An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a...
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