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Patent # Description
2017/0098603 AN ISOLATION DEVICE
An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality...
2017/0098602 Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG...
2017/0098601 MASK AND METAL WIRING OF A SEMICONDUCTOR DEVICE FORMED USING THE SAME
A mask including a mask substrate including a cell exposure region and a peripheral exposure region, the cell exposure region configured to expose a metal...
2017/0098600 WIRING BOARD
A wiring board includes an insulating layer, a first wiring layer, and a second wiring layer. The first wiring layer is formed in a first surface of the...
2017/0098599 OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A manufacturing method of an oxide semiconductor device includes the following steps. An interposer substrate is provided. At least one oxide semiconductor...
2017/0098598 Functionalized interface structure
An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant...
2017/0098597 DIE ATTACHMENT FOR PACKAGED SEMICONDUCTOR DEVICE
A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending...
2017/0098596 APPARATUS AND METHOD OF THREE DIMENSIONAL CONDUCTIVE LINES
An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a...
2017/0098595 DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and...
2017/0098594 PACKAGE INTEGRATED SYNTHETIC JET DEVICE
Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling...
2017/0098593 PACKAGE INTEGRATED SYNTHETIC JET DEVICE
Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling...
2017/0098591 METHOD OF MANUFACTURING ELEMENT CHIP AND ELEMENT CHIP
In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which...
2017/0098590 METHOD OF MANUFACTURING ELEMENT CHIP AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE
In a method of manufacturing an element chip for manufacturing a plurality of element chips by dividing a substrate, where the protruding portions, which are...
2017/0098589 FAN-OUT WAFER LEVEL PACKAGE STRUCTURE
A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the...
2017/0098588 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a...
2017/0098587 METHODS OF MANUFACTURING A PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
2017/0098586 PROTECTING PARTIALLY-PROCESSED PRODUCTS DURING TRANSPORT
Methods, systems and devices for protecting partially processed electronic parts, are disclosed. In some embodiments, a method for protecting electronic parts...
2017/0098585 SOURCE/DRAIN EPITAXIAL ELECTRICAL MONITOR
A source/drain epitaxial electrical monitor and methods of characterizing epitaxial growth through capacitance measurements are provided. The structure...
2017/0098584 DIELECTRIC ISOLATED SiGe FIN ON BULK SUBSTRATE
A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first...
2017/0098583 FORMING A CMOS WITH DUAL STRAINED CHANNELS
The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and...
2017/0098582 FINFET DEVICE
The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a...
2017/0098581 GATE STRUCTURES WITH VARIOUS WIDTHS AND METHOD FOR FORMING THE SAME
Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a...
2017/0098580 Method for Producing a Number of Chip Assemblies and Method for Producing a Semiconductor Arrangement
Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a...
2017/0098579 OPTICAL DEVICE WAFER PROCESSING METHOD
An optical device wafer processing method includes a shield tunnel forming step of applying a pulsed laser beam having a transmission wavelength to a sapphire...
2017/0098578 METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE
A method of fabricating a semiconductor package is disclosed. The method includes forming a plurality of semiconductor chips and a mold layer covering the...
2017/0098577 METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY
A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is...
2017/0098576 SEMICONDUCTOR DEVICE AND FORMATION THEREOF
A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal...
2017/0098575 METHODS FOR DEPOSITING DIELECTRIC BARRIER LAYERS AND ALUMINUM CONTAINING ETCH STOP LAYERS
In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed...
2017/0098574 Integrated Circuit With Conductive Line Having Line-Ends
A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive...
2017/0098573 Methods of Forming an Integrated Circuit Chip Having Two Types of Memory Cells
An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing...
2017/0098572 METHOD AND DEVICE FOR SURFACE TREATMENT OF SUBSTRATES
A method for surface treatment of an at least primarily crystalline substrate surface of a substrate such that by amorphization of the substrate surface, an...
2017/0098571 Warpage Control in the Packaging of Integrated Circuits
A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component...
2017/0098570 SUBSTRATE CARRIER, A PROCESSING ARRANGEMENT AND A METHOD
According to various embodiments, a substrate carrier may include: a substrate-supporting region for supporting a substrate; wherein a first portion of the...
2017/0098569 Wafer Carrier, Method for Manufacturing the Same and Method for Carrying a Wafer
A wafer carrier comprises a first foil, a second foil, and a chamber between the first and the second foil. The first foil has a perforation and is used for...
2017/0098568 Electrostatic Chuck
In accordance with an embodiment of the invention, there is provided an electrostatic chuck comprising an electrode, and a surface layer activated by a voltage...
2017/0098567 METHOD OF FIXING SUBSTRATE USING ELECTROSTATIC CHUCK AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME
An electrostatic chuck and a substrate processing apparatus including the same are disclosed. In one aspect, the electrostatic chuck includes a stage...
2017/0098566 ELECTROSTATIC CHUCK WITH THERMAL CHOKE
Apparatuses, systems, and techniques for providing enhanced electrostatic chucks are provided. Such apparatuses, systems, and techniques may include, for...
2017/0098565 METHODOLOGY FOR CHAMBER PERFORMANCE MATCHING FOR SEMICONDUCTOR EQUIPMENT
Embodiments of the present disclosure provide methodology to match and calibrate processing chamber performance in a processing chamber. In one embodiment, a...
2017/0098564 Substrate Holder Having Integrated Temperature Measurement Electrical Devices
A substrate holder includes a base plate, a bond layer disposed over the base plate, and a ceramic layer disposed over the bond layer. The ceramic layer has a...
2017/0098563 APPARATUS FOR TREATING A SUBSTRATE
An apparatus for treating a substrate includes a chamber including a space in which a substrate is treated, a support member disposed in the chamber and...
2017/0098562 LASER CRYSTALLIZATION APPARATUS FOR CRYSTALLIZING AN AMORPHOUS SILICON THIN FILM
A laser crystallization apparatus includes a laser generator that generates a laser beam including a plurality of line beams that are parallel to each other....
2017/0098561 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A substrate processing apparatus includes a reception part configured to receive film thickness distribution data of a substrate on which a channel region, an...
2017/0098560 SLURRY COMPOSITION FOR CHEMICAL MECHANICAL POLISHING OF GE-BASED MATERIALS AND DEVICES
A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant...
2017/0098559 PLANARIZING PROCESSING METHOD AND PLANARIZING PROCESSING DEVICE
A planarization processing device for polishing a substrate, such as a semiconductor wafer, includes a drive motor that rotates the substrate about a...
2017/0098558 ACID REPLENISHING SYSTEM AND METHOD FOR ACID TANK
An acid replenishing system includes an acid tank, a draining apparatus, an acid replenishing apparatus, and a control unit. The acid tank contains a used acid...
2017/0098557 PLASMA PROCESSING DEVICE
To provide a plasma device that all functions required for a plasma etching process are incorporated into a narrow space of a minimal fabrication manufacturing...
2017/0098556 PURGE AND PUMPING STRUCTURES ARRANGED BENEATH SUBSTRATE PLANE TO REDUCE DEFECTS
A substrate processing system includes a processing chamber including a top surface, a bottom surface and side walls. A substrate support is arranged in the...
2017/0098555 SMALL THERMAL MASS PRESSURIZED CHAMBER
Embodiments described herein generally relate to a processing chamber incorporating a small thermal mass which enable efficient temperature cycling for...
2017/0098554 SUBSTRATE PROCESSING APPARATUS AND METHODS
Apparatus and methods for processing substrates are disclosed. In some embodiments, a substrate processing system includes: a process chamber defining an...
2017/0098553 SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus includes a chamber, a substrate holding part, a substrate rotating mechanism, and a processing liquid supply part. The chamber...
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