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Patent # Description
2017/0104112 PASTE COMPOSITION FOR FORMING SOLAR CELL FRONT ELECTRODE, N-TYPE SOLAR CELL FRONT ELECTRODE FORMED BY USING THE...
The present invention relates to a paste composition for forming a solar cell front electrode, a solar cell front electrode formed by using the composition,...
2017/0104111 SOLAR CELL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A method of forming a solar cell structure is provided, which includes forming a metal electrode on a substrate, forming an absorber layer on the metal...
2017/0104110 PHOTOVOLTAIC DEVICE CONTAINING AN N-TYPE DOPANT SOURCE
Described herein is a method of using the buffer layer of a transparent conductive substrate as a dopant source for the n-type window layer of a photovoltaic...
2017/0104109 SEMICONDUCTOR LIGHT RECEIVING DEVICE
A semiconductor light receiving device includes a substrate, a semiconductor fine line waveguide provided on the substrate, and a light receiving circuit that...
2017/0104108 DOPING AN ABSORBER LAYER OF A PHOTOVOLTAIC DEVICE VIA DIFFUSION FROM A WINDOW LAYER
Methods for doping an absorbent layer of a p-n heterojunction in a thin film photovoltaic device are provided. The method can include depositing a window layer...
2017/0104107 SEMICONDUCTOR DEVICE INCLUDING AN ELECTRICALLY CONDUCTIVE ADHESIVE LAYER AND A BYPASS DIODE IN A CARRIER
A solar cell structure is disclosed. The solar cell structure comprises a carrier having a front side and a P-N junction, a solar cell electrically coupled to...
2017/0104106 DECOUPLING FINFET CAPACITORS
A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon...
2017/0104105 Array Substrate, Display Panel and Display Device
The present invention discloses an array substrate, a display panel and a display device. The array substrate includes a substrate, a gate line and a data line...
2017/0104104 FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
Disclosed are a field effect transistor and method for manufacturing the same, and a display device. The field effect transistor includes: a source and a drain...
2017/0104103 THIN-FILM TRANSISTOR, METHOD FOR FABRICATING THIN-FILM TRANSISTOR, AND DISPLAY DEVICE
Methods of fabricating a thin-film transistor are provided. The methods include forming a gate electrode above a substrate, a gate insulating layer above the...
2017/0104102 Thin Film Transistor and Array Substrate, Manufacturing Methods Thereof, and Display Device
Embodiments of the present invention disclose a thin film transistor and an array substrate, manufacturing methods thereof, and a display device, which relate...
2017/0104101 SEMICONDUCTOR DEVICE INCLUDING DUAL-LAYER SOURCE/DRAIN REGION
A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a...
2017/0104100 FORMING STRESSED EPITAXIAL LAYER USING DUMMY GATES
Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming...
2017/0104099 SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF...
A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the...
2017/0104098 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second...
2017/0104097 LATERAL HIGH VOLTAGE INTEGRATED DEVICES HAVING TRENCN INSULATION FIELD PLATES AND METAL FIELD PLATES
A high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region...
2017/0104096 STRUCTURES AND METHODS OF FABRICATING DUAL GATE DEVICES
First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to...
2017/0104095 VDMOS AND METHOD FOR MAKING THE SAME
A VDMOS includes a substrate; an epitaxial layer; first and second trenches defined in the epitaxial layer; a shielding gate and a control gate formed in the...
2017/0104094 III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS
III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the...
2017/0104093 NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A nitride semiconductor device includes: an electron transit layer including Ga.sub.xIn.sub.1-xN (0<x.ltoreq.1); an electron supply layer formed on the...
2017/0104092 NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A nitride semiconductor device includes: an electron transit layer formed of GaN; an electron supply layer formed on the electron transit layer and to which...
2017/0104091 NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A nitride semiconductor device includes: a first nitride semiconductor layer serving as an electron transit layer; a second nitride semiconductor layer formed...
2017/0104090 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Variation in electrical characteristics of a semiconductor device including an oxide semiconductor is inhibited and the reliability thereof is improved. The...
2017/0104089 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A change in electrical characteristics of a semiconductor device including an oxide semiconductor is prevented, and the reliability of the semiconductor device...
2017/0104088 METHOD AND APPARATUS FOR SOURCE-DRAIN JUNCTION FORMATION IN A FINFET WITH IN-SITU DOPING
A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process...
2017/0104087 METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE
Methods for forming a fin field effect transistor (FinFET) device structure are provided. The method includes providing a first fin structure and a second fin...
2017/0104086 III-V FIN Generation by Lateral Growth on Silicon Sidewall
A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a...
2017/0104085 SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF
This invention provides a semiconductor structure and a forming method thereof. The method for forming the semiconductor structure comprises providing a...
2017/0104084 TRANSISTOR AND METHOD FOR FORMING THE SAME
The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer...
2017/0104083 SURFACE TREATMENT AND PASSIVATION FOR HIGH ELECTRON MOBILITY TRANSISTORS
A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The method includes epitaxially growing a first III-V compound layer...
2017/0104082 FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS
A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall...
2017/0104081 METHOD FOR PREPARING TITANIUM-ALUMINUM ALLOY THIN FILM
A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a...
2017/0104080 Curable Polymeric Materials and Their Use for Fabricating Electronic Devices
The present teachings relate to curable linear polymers that can be used as active and/or passive organic materials in various electronic, optical, and...
2017/0104079 VACUUM TUBE NONVOLATILE MEMORY AND THE METHOD FOR MAKING THE SAME
The present invention provides a vacuum tube nonvolatile memory and the method of manufacturing it. The vacuum tube nonvolatile memory comprises ...
2017/0104078 Semiconductor Device Comprising a Field Electrode
A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a...
2017/0104077 SWITCHING DEVICE WITH CHARGE DISTRIBUTION STRUCTURE
A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer...
2017/0104076 Semiconductor Device
In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The...
2017/0104075 TUNED SEMICONDUCTOR AMPLIFIER
Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two...
2017/0104074 III-V NITRIDE SEMICONDUCTOR DEVICE
In an embodiment, a III-V nitride semiconductor device comprises an AlGaN epitaxial layer and a metal electrode. The AlGaN epitaxial layer is a C-plane n-type...
2017/0104073 TUNED SEMICONDUCTOR AMPLIFIER
Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two...
2017/0104072 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device according to an embodiment includes a SiC semiconductor layer, a gate electrode, a gate insulating film provided between the SiC...
2017/0104071 GRAPHENE DEVICE AND METHOD OF OPERATING THE SAME
A graphene device and a method of operating the same are provided. The graphene device includes: an active layer including a plurality of meta atoms spaced...
2017/0104070 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending...
2017/0104069 APPARATUS AND METHODS FOR FORMING A MODULATION DOPED NON-PLANAR TRANSISTOR
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors...
2017/0104068 THREE-DIMENSIONALLY INTEGRATED CIRCUIT DEVICES INCLUDING OXIDATION SUPPRESSION LAYERS
A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated...
2017/0104067 FinFET Semiconductor Device with Germanium Diffusion Over Silicon Fins
A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor...
2017/0104066 DEVICES WITH MULTIPLE THRESHOLD VOLTAGES FORMED ON A SINGLE WAFER USING STRAIN IN THE HIGH-K LAYER
A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a...
2017/0104065 SEMICONDUCTOR DEVICE INCLUDING DUAL-LAYER SOURCE/DRAIN REGION
A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a...
2017/0104064 Nitride semiconductor device with asymmetric electrode tips
Nitride semiconductor devices having interdigitated array source and drain electrodes arranged like crossed fingers are described. The electric fields extended...
2017/0104063 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active...
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