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Patent # Description
2017/0103961 PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
2017/0103960 SEMICONDUCTOR DEVICE
A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating...
2017/0103959 ANISOTROPIC CONDUCTIVE FILM AND PRODUCTION METHOD OF THE SAME
An anisotropic conductive film that can be produced in high productivity and can reduce a short circuit occurrence ratio has a first conductive particle layer...
2017/0103958 SEMICONDUCTOR PACKAGE
A semiconductor package includes a semiconductor chip mounted on a substrate that has a top surface and a bottom surface opposite to each other, and connection...
2017/0103957 FAN-OUT WAFER-LEVEL PACKAGING USING METAL FOIL LAMINATION
Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to...
2017/0103956 INTEGRATED CIRCUIT PACKAGE
Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include...
2017/0103955 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval...
2017/0103954 STACKING OF MULTIPLE DIES FOR FORMING THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) STRUCTURE
Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second...
2017/0103953 METHOD FOR FABRICATING PACKAGE STRUCTURE
A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic...
2017/0103952 NOISE SHIELDING TECHNIQUES FOR ULTRA LOW CURRENT MEASUREMENTS IN BIOCHEMICAL APPLICATIONS
A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a...
2017/0103951 FAN-OUT SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole and having an...
2017/0103950 RESIN STRUCTURE HAVING ELECTRONIC COMPONENT EMBEDDED THEREIN, AND METHOD FOR MANUFACTURING SAID STRUCTURE
In a resin structure including a resin molded body and a plurality of electronic components embedded in the resin molded body, (i) the resin molded body has a...
2017/0103949 FORMING INTERLAYER DIELECTRIC MATERIAL BY SPIN-ON METAL OXIDE DEPOSITION
A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures...
2017/0103948 INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME
An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first...
2017/0103947 FACETED STRUCTURE FORMED BY SELF-LIMITING ETCH
An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer...
2017/0103946 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and...
2017/0103945 WIRING SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer...
2017/0103944 WIRING SUBSTRATE AND MANUFACTURING METHOD OF WIRING SUBSTRATE
A wiring substrate includes a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern. The first...
2017/0103943 MOLDING COMPOUND WRAPPED PACKAGE SUBSTRATE
A package substrate for chip/chips package wrapped by a molding compound is disclosed. The molding compound functions as a stiffener for the thin film package...
2017/0103942 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a first connection terminal and a protective insulation layer. The first connection terminal is electrically connected to a wiring...
2017/0103941 PACKAGE WITH BI-LAYERED DIELECTRIC STRUCTURE
Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations....
2017/0103940 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the...
2017/0103939 ULTRATHIN ROUTABLE QUAD FLAT NO-LEADS (QFN) PACKAGE
Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device. The method comprises providing a lead frame, the lead...
2017/0103938 SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME
A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring...
2017/0103937 Cooling Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a...
2017/0103936 DBC STRUCTURE USING A SUPPORT INCORPORATING A PHASE CHANGE MATERIAL
DBC type structure, comprising an insulating support (22) coated with at least one conductive zone (20a) able to receive an electronic device, the conductive...
2017/0103935 FLOW PASSAGE MEMBER AND SEMICONDUCTOR MODULE
A flow passage member includes a wall formed of ceramics, a space surrounded by the wall being a flow passage through which a fluid flows, a ratio of an area...
2017/0103934 HEAT SINK FOR A SEMICONDUCTOR CHIP DEVICE
A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the...
2017/0103933 Isolation Rings for Packages and the Method of Forming the Same
A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is...
2017/0103932 SEMICONDUCTOR APPARATUS, STACKED SEMICONDUCTOR APPARATUS, ENCAPSULATED STACKED-SEMICONDUCTOR APPARATUS, AND...
A semiconductor apparatus includes a semiconductor device, on-semiconductor-device metal pad and metal interconnect each electrically connected to the...
2017/0103931 SCAN TESTABLE THROUGH SILICON VIAs
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of...
2017/0103930 STACKED SEMICONDUCTOR APPARATUS BEING ELECTRICALLY CONNECTED THROUGH THROUGH-VIA AND MONITORING METHOD
A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of...
2017/0103929 SEMICONDUCTOR CHIPS HAVING DEFECT DETECTING CIRCUITS
A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer...
2017/0103928 POLISHING METHOD AND POLISHING APPARATUS
A polishing method capable of obtaining an accurate thickness of a silicon layer during polishing of a substrate and determining an accurate polishing end...
2017/0103926 MOUNTING SUBSTRATE AND ELECTRONIC APPARATUS
A mounting substrate according to an embodiment of the present technology includes: a wiring substrate (30); a plurality of light-emitting elements (12)...
2017/0103925 METHOD OF MEASURING A SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
A method for measuring a substrate is provided. The method comprises irradiating a measurement beam into a site box of an identifiable pattern of a substrate,...
2017/0103924 METHOD FOR INSPECTING PHOTORESIST PATTERN
Example embodiments of inventive concepts provide a method for inspecting and/or observing photoresist patterns. The inspecting and/or observing methods may...
2017/0103923 MULTI-GATE TRANSISTOR WITH VARIABLY SIZED FIN
An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a...
2017/0103922 METHOD OF SINGULATING SEMICONDUCTOR WAFER HAVING BACK LAYER
De are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate,...
2017/0103921 PROCESSING METHOD OF OPTICAL DEVICE WAFER
A processing method for optical device wafers includes a shielded tunnel forming step and a dividing step. In the shielded tunnel forming step, a sapphire...
2017/0103920 WAFER PROCESSING METHOD
A wafer processing method including a protective plate attaching step of attaching a protective plate to the front side of a wafer, a support member providing...
2017/0103919 FABRICATION METHOD FOR SEMICONDUCTOR DEVICE
A fabrication method for a semiconductor device is provided. The fabrication method for a semiconductor device includes a semiconductor chip arraying step of...
2017/0103918 Contact Structure of Gate Structure
A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first...
2017/0103917 FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS
A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall...
2017/0103916 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and...
2017/0103915 Method for Interconnect Scheme
A method for fabricating a semiconductor device includes forming a dielectric layer over a substrate, forming an etch-stop-layer (ESL) over the dielectric...
2017/0103914 METHODS FOR FORMATION OF LOW-K ALUMINUM-CONTAINING ETCH STOP FILMS
Dielectric AlO, AlOC, AlON and AlOCN films characterized by a dielectric constant (k) of less than about 10 and having a density of at least about 2.5...
2017/0103913 METHOD FOR MANUFACTURE OF A SEMICONDUCTOR WAFER SUITABLE FOR THE MANUFACTURE OF AN SOI SUBSTRATE, AND SOI...
A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a...
2017/0103912 TOOL FOR MANIPULATING SUBSTRATES, MANIPULATION METHOD AND EPITAXIAL REACTOR
The tool (1) for manipulating substrates in an epitaxial reactor comprises an arm (2), a gripping disc (3) and a ball joint (4); said gripping disc (3) has a...
2017/0103911 CONTROL SYSTEMS EMPLOYING DEFLECTION SENSORS TO CONTROL CLAMPING FORCES APPLIED BY ELECTROSTATIC CHUCKS, AND...
A control system that includes deflection sensors which can control clamping forces applied by electrostatic chucks, and related methods are disclosed. By...
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