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Patent # Description
2017/0133419 OPTICAL DETECTION ELEMENT AND SOLID-STATE IMAGE PICKUP DEVICE
A radiation tolerant optical detection element includes: a p-type base-body region; a gate insulating film provided on an upper surface of the base-body...
2017/0133418 LATCH CIRCUIT, DOUBLE DATA RATE RING COUNTER BASED ON THE LATCH CIRCUIT, HYBRID COUNTING DEVICE, ANALOG-DIGITAL...
Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the...
2017/0133417 IMAGING DEVICE AND IMAGING SYSTEM
An object of the present invention is to prevent a sensitivity difference between pixels. There are disposed plural unit cells each including plural...
2017/0133416 Monolithic Visible-Infrared Focal Plane Array On Silicon
A structure includes a silicon substrate; silicon readout circuitry disposed on a first portion of a top surface of the substrate and a radiation detecting...
2017/0133415 PROTECTION RING FOR IMAGE SENSORS
Some embodiments of the present disclosure provide an image sensor. The image sensor includes a pixel sensor array including a plurality of photosensors...
2017/0133414 DTI FOR BSI IMAGE SENSOR
The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image...
2017/0133413 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A display device comprising a first substrate and a second substrate opposing one another, a thin film transistor and a color filter disposed on the first...
2017/0133412 METHODS OF FORMING PRINTABLE INTEGRATED CIRCUIT DEVICES AND DEVICES FORMED THEREBY
Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the...
2017/0133411 FLEXIBLE DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A flexible display device and a method for manufacturing the same are provided. The method includes providing a rigid sheet having cutting streets, forming a...
2017/0133410 ARRAY SUBSTRATE AND DISPLAY DEVICE
The present disclosure provides an array substrate and a display device that can suppress the adverse effects in display due to difference in gray-scale...
2017/0133409 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number...
2017/0133408 ARRAY SUBSTRATE AND DISPLAY PANEL
An array substrate and a flexible display panel are provided. The array substrate includes a flexible substrate, a thin film transistor, a first metal layer, a...
2017/0133407 Flexible Substrate And Manufacturing Method Thereof, Flexible Display Panel And Flexible Display Device
The invention provide a flexible substrate and manufacturing method thereof, flexible display panel and flexible display device, wherein the flexible substrate...
2017/0133406 METHOD, APPARATUS, AND SYSTEM FOR STACKED CMOS LOGIC CIRCUITS ON FINS
A semiconductor structure, comprising a semiconductor substrate and at least one fin coupled to the semiconductor substrate, wherein the fin comprises at least...
2017/0133405 Z-Inversion Type Display Device and Method of Manufacturing the Same
The present invention provides a Z-inversion type display device comprising a gate line and a data line that intersect with each other to define a pixel area...
2017/0133404 DISPLAY DEVICE
A display device is disclosed, which comprises: a substrate; a first metal conductive layer disposed on the substrate; a semiconductor layer disposed on the...
2017/0133403 ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE
The present disclose provides in some embodiments an array substrate and a method for fabricating the same, and a display device. The array substrate includes...
2017/0133402 AN ARRAY SUBSTRATE AND A DISPLAY DEVICE
One embodiment of the present disclosure provides an array substrate, comprising: a gate line, a data line, and a common electrode layer electrically insulated...
2017/0133401 SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer...
2017/0133400 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate;...
2017/0133399 MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A memory device includes gate electrode layers stacked on top of each other on a substrate, a channel region on a cell region of the substrate and extending...
2017/0133398 VERTICAL MEMORY DEVICE
A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements...
2017/0133397 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
There are provided a 3-D semiconductor device and a manufacturing method thereof. The 3-D semiconductor device includes a substrate extending along a first...
2017/0133396 Memory Devices and Method of Fabricating Same
A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and...
2017/0133395 NOVEL SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of...
2017/0133394 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
To provide a semiconductor device having improved performance. A method of manufacturing the semiconductor device includes forming, after formation of a...
2017/0133393 NON-VOLATILE MEMORY DEVICE
According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive...
2017/0133392 MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending...
2017/0133391 Non-Volatile Semiconductor Memory Device
In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile charge collecting contact, a mobile charge collecting first wiring...
2017/0133390 METHOD FOR PRODUCING ONE-TIME-PROGRAMMABLE MEMORY CELLS AND CORRESPONDING INTEGRATED CIRCUIT
An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode...
2017/0133389 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction...
2017/0133388 NITRIDE-FREE SPACER OR OXIDE SPACER FOR EMBEDDED FLASH MEMORY
In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The...
2017/0133387 Three-Dimensional Static Random Access Memory Device Structures
Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM...
2017/0133386 SEMICONDUCTOR DEVICE, STATIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure,...
2017/0133385 WIRING WITH EXTERNAL TERMINAL
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having...
2017/0133384 SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR
A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The...
2017/0133382 Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory...
2017/0133381 LOOKUP TABLE AND PROGRAMMABLE LOGIC DEVICE INCLUDING LOOKUP TABLE
A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the...
2017/0133380 INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different...
2017/0133379 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so...
2017/0133376 FIN SCULPTING AND CLADDING DURING REPLACEMENT GATE PROCESS FOR TRANSISTOR CHANNEL APPLICATIONS
Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for...
2017/0133375 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate...
2017/0133374 Integrated Circuit Having a Vertical Power MOS Transistor
A device includes a vertical transistor comprising a first buried layer over a substrate, a first well over the first buried layer, a first gate in a first...
2017/0133373 INTEGRATED CIRCUITS HAVING MULTIPLE GATE DEVICES WITH DUAL THRESHOLD VOLTAGES AND METHODS FOR FABRICATING SUCH...
Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An...
2017/0133372 FORMING MOSFET STRUCTURES WITH WORK FUNCTION MODIFICATION
A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region...
2017/0133370 SEMICONDUCTOR DEVICE
A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns;...
2017/0133368 HIGH BANDGAP SCHOTTKY CONTACT LAYER DEVICE
A high bandgap Schottky contact layer device and methods for producing same are provided herein. According to one aspect, a high bandgap Schottky contact layer...
2017/0133367 SYSTEM ON CHIP
Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a...
2017/0133366 MOS TRANSISTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE WITH VERTICALLY AND HORIZONTALLY-ELONGATED METAL...
Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions...
2017/0133365 POWER RAIL INBOUND MIDDLE OF LINE (MOL) ROUTING
In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact...
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