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Patent # Description
2017/0133314 PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF
A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top...
2017/0133313 STRIP-SHAPED SUBSTRATE FOR PRODUCING CHIP CARRIERS, ELECTRONIC MODULE WITH A CHIP CARRIER OF THIS TYPE,...
A strip-shaped substrate made from a film includes a plurality of units for producing chip carriers. Each unit has a chip island for fixing a semiconductor...
2017/0133312 Semiconductor Device
The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering...
2017/0133311 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element...
2017/0133310 SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various...
2017/0133309 FAN-OUT SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME
A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite...
2017/0133308 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF
The semiconductor device includes a multi-layered substrate having an insulating plate and a circuit plate, a semiconductor chip having a front surface...
2017/0133307 PACKAGING SUBSTRATE FOR SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND METHOD
A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second...
2017/0133306 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled...
2017/0133305 3D SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES
A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement...
2017/0133304 Low Profile Leaded Semiconductor Package
In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the...
2017/0133303 SEMICONDUCTOR DEVICE AND A METHOD OF MAKING A SEMICONDUCTOR DEVICE
A semiconductor device and a method of making the same. The device includes a substrate mounted on a carrier, the substrate comprising a High Electron Mobility...
2017/0133301 RECESSED LEAD LEADFRAME PACKAGES
Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads...
2017/0133300 LEADFRAME AND SEMICONDUCTOR DEVICE
A semiconductor device includes a leadframe, a semiconductor chip, and an encapsulation resin encapsulating the leadframe and the semiconductor chip. The...
2017/0133299 SEMICONDUCTOR DEVICE HAVING REPAIRABLE PENETRATION ELECTRODE
A semiconductor device having a repairable penetration electrode is provided. The semiconductor device having the repairable penetration electrode includes...
2017/0133297 ASSEMBLY OF AN INTEGRATED CIRCUIT CHIP AND OF A PLATE
An assembly includes an integrated circuit chip and a plate with at least one heat removal channel arranged between the chip and the plate. Metal sidewalls are...
2017/0133295 SEMICONDUCTOR DEVICE WITH HIGH THERMAL CONDUCTIVITY SUBSTRATE AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a process of forming a semiconductor device with a high thermal conductivity substrate. According to an exemplary process, a...
2017/0133294 SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
A semiconductor module (100) has a first insulating substrate (11); a first conductor layer (12) provided on a mounting surface of the first insulating...
2017/0133293 ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME
An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on...
2017/0133292 HYBRID PARYLENE-METAL OXIDE LAYERS FOR CORROSION RESISTANT COATINGS
Described herein is a composite coating on a substrate including a parylene layer deposited on a substrate surface of a substrate, a metal oxide layer covering...
2017/0133291 SEMICONDUCTOR MODULE COMPRISING AN ENCAPSULATING COMPOUND THAT COVERS AT LEAST ONE SEMICONDUCTOR COMPONENT
A semiconductor module (10) contains a ceramic interconnect device (50) having at least one semiconductor component (20). The at least one semiconductor...
2017/0133290 PACKAGE STRUCTURE
The invention provides a package structure which includes a substrate, at least one chip module, and a housing. The at least one chip module is located on the...
2017/0133289 SEMICONDUCTOR CHIP
According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the...
2017/0133288 BOARD FOR ELECTRONIC COMPONENT PACKAGE, ELECTRONIC COMPONENT PACKAGE, AND METHOD OF MANUFACTURING BOARD FOR...
A board for an electronic component package includes a wiring part on which an electronic component is disposed, wherein the wiring part includes an insulating...
2017/0133287 TEST STRUCTURES AND METHOD OF FORMING AN ACCORDING TEST STRUCTURE
The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and...
2017/0133286 SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have...
2017/0133285 HEAT TREATMENT SYSTEM, HEAT TREATMENT METHOD, AND PROGRAM
A heat treatment system includes a heat treatment condition storing unit that stores a heat treatment condition with respect to a doping processing and a...
2017/0133284 SMART IN-SITU CHAMBER CLEAN
A microelectronic device is formed using a fabrication tool such as a plasma thin film deposition tool or a plasma etch tool. A smart in-situ chamber clean...
2017/0133283 SENSOR AND ADJUSTER FOR A CONSUMABLE
An apparatus for use in a processing chamber is provided. A consumable is within the processing chamber. A scale is positioned to measure a mass of the...
2017/0133282 Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages
An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure...
2017/0133281 METHOD AND ARRANGEMENT FOR ANALYZING A SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT
According to the improved concept, a method for analyzing a semiconductor element comprising polymer residues located on a surface of the semiconductor element...
2017/0133280 METHOD FOR FABRICATING SUBSTRATE
A method for fabricating a substrate includes forming a first substrate including a thin film transistor array, and inspecting a first surface of an inspecting...
2017/0133279 Inverters and Manufacturing Methods Thereof
Inverters and methods of manufacture thereof are disclosed. In some embodiments, an inverter includes a substrate and a first tunnel FET (TFET) disposed over...
2017/0133278 ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs
Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different...
2017/0133276 TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes...
2017/0133275 SEMICONDUCTOR DEVICES HAVING MULTIPLE GATE STRUCTURES AND METHODS OF MANUFACTURING SUCH DEVICES
A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate...
2017/0133274 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a...
2017/0133273 POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE IN DUAL STRESS LINER PROCESS FLOW
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and...
2017/0133272 FORMING MOSFET STRUCTURES WITH WORK FUNCTION MODIFICATION
A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region...
2017/0133271 Method to produce a semiconductor wafer for versatile products
Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to...
2017/0133269 WAFER PROCESSING METHOD
A laser beam is applied to the front side of a wafer along division lines, to form grooves having a depth corresponding to a finished thickness of device...
2017/0133268 CHAMFERLESS VIA STRUCTURES
Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric...
2017/0133267 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material...
2017/0133266 METHODS OF FORMING CONTACT HOLES USING PILLAR MASKS AND MASK BRIDGES
A fabrication method of the semiconductor device comprises forming an isolation layer and an active region, which is defined by the isolation layer, on a...
2017/0133265 ADVANCED MOSFET CONTACT STRUCTURE TO REDUCE METAL-SEMICONDUCTOR INTERFACE RESISTANCE
A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at...
2017/0133264 Semiconductor Device and Method for Fabricating the Same
A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a...
2017/0133263 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device...
2017/0133262 METTHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the...
2017/0133261 DEEP TRENCH ISOLATION WITH TANK CONTACT GROUNDING
An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite,...
2017/0133260 Lift Pin Assembly and Associated Methods
A substrate lift pin assembly includes a tubular support member connected to a bottom of a pedestal beneath a lift pin through-hole. The tubular support member...
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