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Patent # Description
2017/0132162 APPARATUSES AND METHODS FOR ASYMMETRIC BI-DIRECTIONAL SIGNALING INCORPORATING MULTI-LEVEL ENCODING
Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and...
2017/0132161 I/O REQUEST PROCESSING METHOD AND STORAGE SYSTEM
An input output (I/O) request processing method is applied to a storage system and includes: receiving an I/O request, where the I/O request carries a size and...
2017/0132160 MEMORY TAMPER DETECTION
A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor, by (1) periodically...
2017/0132159 SYSTEM AND METHOD FOR INTERCEPT OF UEFI BLOCK I/O PROTOCOL SERVICES FOR BIOS BASED HARD DRIVE ENCRYPTION SUPPORT
An information handling system and method performs Unified Extensible Firmware Interface (UEFI) interception and pre-processing of data associated with block...
2017/0132158 PROTECTING A MEMORY FROM UNAUTHORIZED ACCESS
A method includes generating a set of virtual-machine-specific (VMS) encryption keys for a dedicated virtual machine, storing the set of VMS encryption keys in...
2017/0132157 METHOD AND APPARATUS FOR SECURING AND CONTROLLING INDIVIDUAL USER DATA
A system includes a processor configured to transfer a newly generated encryption key for a newly paired device to the device and utilize the encryption key to...
2017/0132156 PROTECTING A MEMORY FROM UNAUTHORIZED ACCESS
A method includes generating a set of virtual-machine-specific (VMS) encryption keys for a dedicated virtual machine, storing the set of VMS encryption keys in...
2017/0132155 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT
A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit...
2017/0132154 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR MANAGING CACHE DESTAGE RATES AND...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132153 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR MANAGING CACHE LINE UPDATES FOR...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132152 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR IDENTIFICATION OF DATA AGE IN STORAGE...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132151 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR DESTAGE OPERATIONS FROM STORAGE WRITE...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132150 Memory Controller For Selective Rank Or Subrank Access
A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and...
2017/0132149 TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASSIDE BUFFER READ
A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data...
2017/0132148 Memory Management Method and Device and Memory Controller
A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page...
2017/0132147 CACHE WITH ADDRESS SPACE MAPPING TO SLICE SUBSETS
A processing device includes a cache implementing a set of at least three cache slices. Each cache slice is to store a corresponding set of cache lines. The...
2017/0132146 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR SIMULTANEOUS READ AND DESTAGE...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132145 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR READS WITH PARTIAL READ HITS FROM...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132144 ENERGY-EFFICIENT DYNAMIC DRAM CACHE SIZING
Techniques described herein generally include methods and systems related to dynamic cache-sizing used to reduce the energy consumption of a DRAM cache in a...
2017/0132143 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR MERGING DATA WITH EXISTING DATA ON...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132142 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR WRITES TO STORAGE WRITE CACHE
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132141 Intelligent Caching of Responses in a Cognitive System
Mechanism are provided for implementing an intelligent response caching engine. The mechanisms receive a set of attributes to be used to cache responses to...
2017/0132139 INSTRUCTION STREAM MODIFICATION FOR MEMORY TRANSACTION PROTECTION
Execution of a set of instructions within a transaction is prevented. A processor identifies a first set of instructions in an instruction stream of a...
2017/0132137 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR READS FROM STORAGE WRITE CACHE
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2017/0132136 Non-Volatile Memory Cache Performance Improvement
In order to provide a more efficient persistent storage device, one or more long-term storage media are included along with a non-volatile memory. In one...
2017/0132135 DEFERRED RESPONSE TO A PREFETCH REQUEST
Preventing a prefetch memory operation from causing a transaction to abort by receiving by a local processor a prefetch request from a remote processor....
2017/0132134 PREFETCH INSENSITIVE TRANSACTIONAL MEMORY
Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A...
2017/0132133 PREFETCH PROTOCOL FOR TRANSACTIONAL MEMORY
Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch...
2017/0132131 Combined Transparent/Non-Transparent Cache
In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit...
2017/0132130 CACHE COHERENCY FOR DIRECT MEMORY ACCESS OPERATIONS
Methods, apparatus, systems and articles of manufacture are disclosed to maintain cache coherency. Examples disclosed herein involve, in response to receiving,...
2017/0132129 STORAGE SYSTEM AND MONITOR DEVICE
A storage system includes control devices and a second processor. The second processor determines a number of abnormal batteries when an abnormality has...
2017/0132126 SELECTION AND PLACEMENT OF VOLUMES IN A STORAGE SYSTEM USING STRIPES
Provided are a computer program product, system, and method for determining the location for volumes of data being initially stored within a storage space,...
2017/0132125 SELECTIVE DATA RECYCLING IN NON-VOLATILE MEMORY
Embodiments are directed to methods of classifying a flash memory block of N-level cells into sub-blocks. The N-level cells can store N bits of data. In some...
2017/0132124 PREFETCH INSENSITIVE TRANSACTIONAL MEMORY
Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A...
2017/0132123 DYNAMIC MANAGEMENT AND CONTROL OF TEST FEATURES IN NATIVE APPLICATIONS
Techniques are described herein for enhancing software application development and software design-for-test (DFT) technology by facilitating dynamic management...
2017/0132122 SYSTEM PARAMETER PROCESSING METHOD, DEVICE AND SYSTEM
The present disclosure discloses system parameter processing method, device and system. The method includes receiving a parameter processing instruction input...
2017/0132121 INCREMENTAL CODE COVERAGE ANALYSIS USING AUTOMATIC BREAKPOINTS
A portion is selected from a code for code coverage analysis. The portion is not directly referenceable by another portion of the code. An instruction is...
2017/0132120 COMPATIBILITY CHECK FOR CONTINUOUS GLUCOSE MONITORING APPLICATION
Disclosed are systems, methods, and articles for determining compatibility of a mobile application and operating system on a mobile device. In some aspects, a...
2017/0132119 METHOD AND DEVICE FOR RETRIEVING TEST CASE BASED ON CODE COVERAGE
Embodiments of the present invention relate to a method and a device for obtaining test cases based on a code coverage. The method comprises creating a mapping...
2017/0132118 METHOD AND APPARATUS FOR TESTING SOFTWARE FOR AUTONOMOUS VEHICLES
A method and an apparatus for testing software for autonomous vehicles by means of a loop simulation involves hardware in the form of one or more real...
2017/0132117 METHOD AND DEVICE FOR GENERATING TEST CASES FOR AUTONOMOUS VEHICLES
Test cases for autonomous vehicles are generated automatically by using data which have been collected from vehicles participating in public road traffic. A...
2017/0132116 Methods Circuits Apparatuses Systems and Associated Computer Executable Code for Generating a Software Unit Test
Disclosed are methods, circuits, apparatuses, systems and associated computer executable code for generating a unit test. According to some embodiments, there...
2017/0132115 CONSTRAINT EXTRACTION FROM NATURAL LANGUAGE TEXT FOR TEST DATA GENERATION
A device may obtain text to be processed to extract constraints corresponding to an object in the text. The constraints may define values permitted to be...
2017/0132114 EXTRACTION OF PROBLEM DIAGNOSTIC KNOWLEDGE FROM TEST CASES
Embodiments of the present invention enable users to extract knowledge from testing scenarios performed during application development, and later employ that...
2017/0132113 EXTRACTION OF PROBLEM DIAGNOSTIC KNOWLEDGE FROM TEST CASES
Embodiments of the present invention enable users to extract knowledge from testing scenarios performed during application development, and later employ that...
2017/0132112 TEST METHOD AND DEVICE FOR BUSINESS SYSTEM
The present disclosure provides a test method and device for a business system. The method includes: acquiring a preset page address; sending a first control...
2017/0132111 MONITORING MOBILE APPLICATION PERFORMANCE
Aspects of the subject disclosure are directed towards monitoring application performance during actual use, particularly mobile application performance....
2017/0132110 DYNAMIC RANKING OF PERFORMANCE ISSUES FOR APPLICATIONS
Identification and dynamic ranking of performance issues. For an instance of a performance anti-pattern, identifying and recording information relating to a...
2017/0132109 AUTOMATIC COLLECTION AND PRESENTATION OF RUNTIME DATA SEMANTICS
An approach for collection and presentation of runtime data semantics. At least one of code-coverage history, system runtime history and code version...
2017/0132108 Debugging Parallel Graphical Program Code
System and method for debugging a graphical program. A graphical program may be received, e.g., from storage, from another process or device, etc. The program...
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