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Patent # Description
2017/0141146 IMAGE SENSORS WITH IMPROVED SURFACE PLANARITY
A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery...
2017/0141145 IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME
An image sensor structure and a method for forming the same are provided. The image sensor structure includes a substrate having a front side and a backside...
2017/0141144 SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS
The present disclosure relates to a semiconductor device and an electronic apparatus capable of reducing a leak current of a PN junction region. In a Si...
2017/0141143 IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME
An image sensor includes a semiconductor substrate integrated with at least one of a first photo-sensing device that may sense a first wavelength spectrum of...
2017/0141142 OPTOELECTRONICS AND CMOS INTEGRATION ON GOI SUBSTRATE
A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an...
2017/0141141 MANUFACTURE METHOD OF DUAL GATE OXIDE SEMICONDUCTOR TFT SUBSTRATE AND STRUCTURE THEREOF
The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate...
2017/0141140 MANUFACTURE METHOD OF DUAL GATE TFT SUBSTRATE AND STRUCTURE THEREOF
The present invention provides a manufacture method of a dual gate TFT substrate and a structure thereof. The manufacture method of a dual gate TFT substrate,...
2017/0141139 LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME
An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array...
2017/0141138 LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME
An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first...
2017/0141137 Manufacturing Method and Structure thereof of TFT Backplane
The disclosure provides a manufacturing method and a structure thereof of a TFT backplane. In the manufacturing method of the TFT backplane, after a...
2017/0141136 Display Module Manufacturing Method and Display Module
A display module substrate and a manufacturing method thereof are provided. The display module substrate includes a substrate body and a plurality of signal...
2017/0141135 CARRIER SUBSTRATE HAVING A PLURALITY OF FLUID PASSAGES AND METHOD OF FABRICATING DISPLAY APPARATUS UTILIZING...
The present application discloses a method of fabricating a display apparatus, comprising providing a carrier substrate comprising a base substrate and an...
2017/0141134 Butted Body Contact for SOI Transistor
Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the...
2017/0141133 DISPLAY PANEL
A display panel is provided, which includes a first substrate, a first insulating layer on the first substrate, a semiconductor layer on the first insulating...
2017/0141132 Pixel Unit and Method for Producing the Same, Array Substrate and Display Apparatus
The present disclosure provides a pixel unit and a method for producing the same, an array substrate and a display apparatus. The pixel unit includes: a thin...
2017/0141131 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a substrate, a semiconductor layer, a source electrode, a drain electrode, first insulating...
2017/0141130 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
To provide a highly reliable semiconductor device that is suitable for miniaturization and an increase in density. The semiconductor device includes a first...
2017/0141129 DISPLAY PANEL INCLUDING STATIC ELECTRICITY PREVENTING PATTERN AND DISPLAY DEVICE HAVING THE SAME
A display device comprising a display panel that includes an active area, the active area including a data line positioned on a substrate in a first direction...
2017/0141128 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate...
2017/0141127 METHOD FOR MANUFACTURING TFT SUBSTRATE AND STRUCTURE THEREOF
The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate uses a...
2017/0141126 Butted Body Contact for SOI Transistor
Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower...
2017/0141125 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Provided are a semiconductor device and a method of manufacturing the semiconductor device which enable a hard copy of a reconfigurable circuit, which employs...
2017/0141123 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a first...
2017/0141122 A THREE-DIMENSIONAL MEMORY DEVICE
According to one embodiment, the plurality of contact vias extend in the stacking direction in the insulating layer, and are in contact with the end parts of...
2017/0141121 VERTICAL MEMORY BLOCKS AND RELATED DEVICES AND METHODS
Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a...
2017/0141120 DISCRETE STORAGE ELEMENT FORMATION FOR THIN-FILM STORAGE DEVICE
Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion...
2017/0141119 Integrated Structures and Methods of Forming Integrated Structures
Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has...
2017/0141118 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
A nonvolatile semiconductor storage device includes a memory string including a plurality of memory cells connected in series with each other, and a select...
2017/0141117 MEMORY DEVICE WITH MANUFACTURABLE CYLINDRICAL STORAGE NODE
A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a...
2017/0141116 Multi-Die Fine Grain Integrated Voltage Regulation
A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more...
2017/0141115 PRINTED CAPACITORS
A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of...
2017/0141114 SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an...
2017/0141113 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second...
2017/0141112 Multi-Gate Device and Method of Fabrication Thereof
A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first...
2017/0141111 FINFET DEVICES AND METHODS OF FORMING THE SAME
FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The...
2017/0141110 DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME
Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor...
2017/0141109 SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS
Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having...
2017/0141108 FINFET ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an air gap and a dielectric cap layer. The...
2017/0141107 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate...
2017/0141106 FIN FIELD EFFECT TRANSISTOR, SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is...
2017/0141105 SEMICONDUCTOR DEVICE COMPRISING A FIRST TRANSISTOR AND A SECOND TRANSISTOR
A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact...
2017/0141104 METHOD AND STRUCTURE FOR SEMICONDUCTOR MID-END-OF-LINE (MEOL) PROCESS
A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an...
2017/0141103 SEMICONDUCTOR DEVICE
An influence of a gate interference is suppressed and a reverse recovery property of a diode is improved. A diode includes a diode region located between the...
2017/0141102 GATE STACK INTEGRATED METAL RESISTORS
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate...
2017/0141101 METHOD OF IMPROVING BIPOLAR DEVICE SIGNAL TO NOISE PERFORMANCE BY REDUCING THE EFFECT OF OXIDE INTERFACE...
An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base...
2017/0141100 ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION
Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is...
2017/0141099 SEMICONDUCTOR DEVICE
Connection patterns of plural diodes include a first series connection pattern and a second series connection pattern. The first series connection pattern...
2017/0141098 FinFET-Based ESD Devices and Methods for Forming the Same
A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of...
2017/0141097 TVS Structures for High Surge AND Low Capacitance
A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device...
2017/0141096 PROXIMITY COUPLING OF INTERCONNECT PACKAGING SYSTEMS AND METHODS
Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed...
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