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Patent # Description
2017/0141095 Package with SoC and Integrated Memory
A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The...
2017/0141094 MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF
A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge...
2017/0141093 SEMICONDUCTOR APPARATUS INSTALLING PASSIVE DEVICE
A semiconductor apparatus that comprises a package, an active device, and a passive device is disclosed. The package includes a metal base, a shell, and a lid....
2017/0141092 SEMICONDUCTOR PACKAGE
A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface,...
2017/0141091 DISPLAY MODULE AND SYSTEM APPLICATIONS
A display module and system applications including a display module are described. The display module may include a display substrate including a front...
2017/0141090 SEMICONDUCTOR DEVICES FOR INTEGRATION WITH LIGHT EMITTING CHIPS AND MODULES THEREOF
A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost...
2017/0141089 Power Semiconductor Arrangement Having a Plurality of Power Semiconductor Switching Elements and Reduced...
A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current...
2017/0141088 THREE LAYER STACK STRUCTURE
Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level...
2017/0141087 PACKAGED DEVICES WITH MULTIPLE PLANES OF EMBEDDED ELECTRONIC DEVICES
A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The...
2017/0141086 SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal...
2017/0141085 MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
2017/0141084 MICROELECTRONIC PACKAGES HAVING EMBEDDED SIDEWALL SUBSTRATES AND METHODS FOR THE PRODUCING THEREOF
Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method...
2017/0141083 Packaged Microelectronic Device for a Package-on-Package Device
Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device ("PoP") with enhanced tolerance for warping. In...
2017/0141082 ELECTRIC POWER CONVERTER
An electric power converter includes a semiconductor module, an electronic component, a plurality of cooling tubes, a case, a main pressure member for pressing...
2017/0141081 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a...
2017/0141080 Semiconductor Device and Method of Manufacture
A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two...
2017/0141079 SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least...
2017/0141078 SPLIT BALL GRID ARRAY PAD FOR MULTI-CHIP MODULES
A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each...
2017/0141077 ORGANIC ELECTROLUMINESCENT DEVICE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE
The embodiments of the present invention provide an organic electroluminescent device, manufacturing method thereof and display device, which relate to the...
2017/0141076 LIGHT EMITTING DEVICE
A plurality of transmissive organic EL panels in a light emitting device each include: a first transparent substrate; a second transparent substrate; an...
2017/0141075 PROCESS OF FORMING SEMICONDUCTOR DEVICE
A process of forming a semiconductor device is disclosed, where the semiconductor device provides a base and a semiconductor chip that is mounted on the base...
2017/0141074 METAL PREPARATION FOR CONNECTING COMPONENTS
A metal preparation is provided which contains (A) 40 to <80% by weight of at least one metal in the form of particles having a coating that contains at...
2017/0141073 Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps
Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package...
2017/0141072 OPTIMIZED SOLDER PADS FOR MICROELECTRONIC COMPONENTS
A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the...
2017/0141071 METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE
Provided is a method of fabricating a semiconductor package. The method includes providing a package substrate including a pad, mounting a semiconductor chip...
2017/0141070 Clamping Assembly Having A Spring System
A clamping assembly includes a configuration of mechanically clamped components that lie on top of one another to form a stack, a spring system and a clamping...
2017/0141069 DISTRIBUTION OF ELECTRONIC CIRCUIT POWER SUPPLY POTENTIALS
An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated...
2017/0141068 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device which includes a first member and a second member joined to the first member includes: a) producing...
2017/0141067 Metal Bump Joint Structure and Methods of Forming
A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further...
2017/0141066 ELECTRONIC DEVICE
An electronic device includes a mount board, first and second electronic components flip-chip mounted on a surface of the mount board with bumps interposed...
2017/0141065 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging...
2017/0141064 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging...
2017/0141063 ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME
An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal...
2017/0141062 COPPER-CONTAINING C4 BALL-LIMITING METALLURGY STACK FOR ENHANCED RELIABILITY OF PACKAGED STRUCTURES AND METHOD...
The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal...
2017/0141061 ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS
Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on...
2017/0141060 Post-Passivation Interconnect Structure and Method of Forming Same
A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the...
2017/0141059 Conductive External Connector Structure and Method of Forming
External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical...
2017/0141058 METHOD AND APPARATUS FOR FORMING BACKSIDE DIE PLANAR DEVICES AND SAW FILTER
Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on...
2017/0141057 SEMICONDUCTOR DEVICE PACKAGE, ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICES USING WAFER...
A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist...
2017/0141056 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a die including a die pad disposed over the die; a conductive member disposed over and electrically connected with the die...
2017/0141055 Chip Packages and Methods of Manufacture Thereof
A chip package may include a die and a redistribution structure over the die. The redistribution structure may include a die, a redistribution structure over...
2017/0141054 Package with Solder Regions Aligned to Recesses
A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer...
2017/0141053 Integrated Fan-Out Structure and Method of Forming
Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer...
2017/0141052 SEAL RINGS STRUCTURES IN SEMICONDUCTOR DEVICE INTERCONNECT LAYERS AND METHODS OF FORMING THE SAME
An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a...
2017/0141051 Methods and Apparatus of Guard Rings for Wafer-Level-Packaging
A method of forming a semiconductor device includes forming a passivation layer on top of a guard ring and an active area of a circuit device, forming a...
2017/0141050 Printed Circuit Board
A printed circuit board includes chip regions on which semiconductor chips are mounted, and a scribe region surrounding each of the chip regions. The scribe...
2017/0141049 Wafer Edge Shape for Thin Wafer Processing
A wafer that includes a front surface, a back surface, and an edge between the front surface and the back surface having a curved edge profile between an edge...
2017/0141048 RADIATION-HARD ELECTRONIC DEVICE AND METHOD FOR PROTECTING AN ELECTRONIC DEVICE FROM IONIZING RADIATION
A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the...
2017/0141047 MICROWAVE AND MILLIMETER WAVE PACKAGE
A package includes a conductor base plate having a element fixed to an upper surface thereof, a side wall provided on the conductor base plate to surround the...
2017/0141046 SEMICONDUCTOR DEVICE WITH AN ELECTROMAGNETIC INTERFERENCE (EMI) SHIELD
A method for forming a semiconductor device with an electromagnetic interference shield is disclosed and may include coupling a semiconductor die to a first...
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