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Patent # Description
2017/0141045 Semiconductor Package and Method of Manufacturing the Same
The present invention relates to a semiconductor package and a method of manufacturing the same. Specifically, the present invention relates to a semiconductor...
2017/0141044 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive...
2017/0141043 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Disclosed are a semiconductor package including a through via and a method of manufacturing the same. The semiconductor package includes a frame having an...
2017/0141042 'RDL-First' Packaged Microelectronic Device for a Package-on-Package Device
Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device ("PoP") with enhanced tolerance for warping. In...
2017/0141041 SEMICONDUCTOR PACKAGE ASSEMBLY
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first...
2017/0141040 STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely...
2017/0141039 METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
2017/0141038 SELF-ALIGNED CONTACT PROCESS ENABLED BY LOW TEMPERATURE
Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The...
2017/0141037 METHODS AND STRUCTRUES OF NOVEL CONTACT FEATURE
A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin...
2017/0141036 PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric...
2017/0141035 PATTERN PLACEMENT ERROR COMPENSATION LAYER
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric...
2017/0141034 POWER LINE LAYOUT STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A power line layout structure of a semiconductor device and a method for forming the same are disclosed. The power line layout structure of the semiconductor...
2017/0141033 Active Atomic Reservoir For Enhancing Electromigration Reliability In Integrated Circuits
An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting...
2017/0141032 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over...
2017/0141031 SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF
Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor...
2017/0141029 Enhancing Integrated Circuit Density with Active Atomic Reservoir
An integrated circuit (IC) comprises first and second conductors in one layer of the IC, wherein the first conductor is oriented along a first direction, the...
2017/0141028 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a conductive structure, a dielectric layer, and a plurality of conductive features. The dielectric layer is present on the...
2017/0141027 CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric...
2017/0141026 SERIES MIM STRUCTURES
The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip...
2017/0141025 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
A semiconductor device may include a first metal line; a second metal line; a first insulating layer formed between the first metal line and the second metal...
2017/0141024 LAND SIDE AND DIE SIDE CAVITIES TO REDUCE PACKAGE Z-HEIGHT
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die...
2017/0141023 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer...
2017/0141022 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A terminal pressing frame of a semiconductor device is disposed so as to form a first gap partially from the bottom surface of an L-shaped leg portion of an...
2017/0141021 MAGNETIC ALIGNMENT FOR FLIP CHIP MICROELECTRONIC DEVICES
Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic...
2017/0141020 STIFFENED WIRES FOR OFFSET BVA
A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the...
2017/0141019 SEMICONDUCTOR DEVICE, CORRESPONDING METHODS OF PRODUCTION AND USE AND CORRESPONDING APPARATUS
A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of...
2017/0141018 Semiconductor Device and Alternator Using Same
Provided are a semiconductor device realized easily at low cost without requiring a complicated manufacturing process, and an alternator using the same. The...
2017/0141017 SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME
In one embodiment, methods for making semiconductor devices are disclosed.
2017/0141016 CAVITY PACKAGE WITH DIE ATTACH PAD
A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The...
2017/0141015 Driving Chip Package and Display Device Including the Same
A display device includes a display panel and a chip-on-film (COF) bonded to the display panel. The chip-on-film includes a film on which a driving chip is...
2017/0141014 SEMICONDUCTOR PACKAGE WITH INTEGRATED HEATSINK
One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes...
2017/0141013 SYSTEMS AND METHODS FOR COUPLING A SEMICONDUCTOR DEVICE OF AN AUTOMATION DEVICE TO A HEAT SINK
A system includes a heat sink, a semiconductor device, a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device,...
2017/0141012 SEMICONDUCTOR MODULE
A semiconductor module includes case that houses a semiconductor device therein and a fastener that is connected at one end thereof to the case. The fastener...
2017/0141011 JOINED BODY MANUFACTURING METHOD, MULTILAYER JOINED BODY MANUFACTURING METHOD, POWER-MODULE SUBSTRATE...
A joined body manufacturing method includes: a laminating step for forming a laminated body in which either a copper circuit substrate (first member) or a...
2017/0141010 METHOD FOR PRODUCING CERAMIC-ALUMINUM BONDED BODY, METHOD FOR PRODUCING POWER MODULE SUBSTRATE,...
A method for producing a ceramic-aluminum bonded body obtained by bonding a ceramic member and an aluminum member, the aluminum member before bonding being...
2017/0141009 HEAT DIFFUSION SHEET
A heat diffusion sheet 2 has a configuration in which a composite adhesive film is formed on a surface of a graphite sheet 10 having a thickness of 300 .mu.m...
2017/0141008 HEAT SPREADERS WITH INTEGRATED PREFORMS
Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may...
2017/0141007 FILLER COMPOSITIONS AND UNDERFILL COMPOSITIONS AND MOLDING COMPOUNDS INCLUDING THE SAME FOR PREPARING...
The present disclosure relates to a filler composition for a semiconductor package. The filler composition comprises carbon and silica.
2017/0141006 APPARATUS AND METHOD TO MONITOR DIE EDGE DEFECTS
Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a...
2017/0141005 METHOD OF TREATING A MICROELECTRONIC SUBSTRATE USING DILUTE TMAH
Embodiments of the invention provide a method for treating a microelectronic substrate with dilute TMAH. In the method, a microelectronic substrate is received...
2017/0141004 OPTO-ACOUSTIC METROLOGY OF SIGNAL ATTENUATING STRUCTURES
Methods and systems for manufacturing and analyzing interconnect structures in integrated circuit (IC) devices. The methods include forming an interconnect...
2017/0141003 ELECTRMIGRATION SIGN-OFF METHODOLOGY
The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of...
2017/0141002 Systems and Methods for Frequency Modulation of Radiofrequency Power Supply for Controlling Plasma Instability
A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode....
2017/0141001 Systems and Methods for Detection of Plasma Instability by Optical Diagnosis
A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode....
2017/0141000 Systems and Methods for Detection of Plasma Instability by Electrical Measurement
A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode....
2017/0140999 Fabrication Of Thin-Film Encapsulation Layer For Light Emitting Device
An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink...
2017/0140998 SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION STRUCTURES
A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at...
2017/0140997 FINFET AND METHOD OF FORMING FIN OF THE FINFET
A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first...
2017/0140996 Horizontal Gate-All-Around Device Having Wrapped-Around Source and Drain
A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The...
2017/0140995 FINFET DEVICES
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of...
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