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Patent # Description
2017/0140843 NUCLEAR REACTOR FLOW PATH SEALING SYSTEMS AND SEALS
Seals are positioned between abutting nuclear reactor components. Example seals are held in position by gravity, grooves, retainers, direct joining, or other...
2017/0140842 Subcritical Reactivity Monitor Utilizing Prompt Self-Powered Incore Detectors
A subcritical reactivity monitor that utilizes one or more primarily gamma sensitive (prompt responding) self-powered detector style radiation measurement...
2017/0140841 NUCLEAR FUEL ROD FOR FAST REACTORS INCLUDING METALLIC FUEL SLUG COATED WITH PROTECTIVE COATING LAYER AND...
Provided are a nuclear fuel rod for fast reactors that includes a metallic fuel slug coated with a protective coating layer and a fabrication method thereof....
2017/0140840 MEMORY DEVICE AND A MEMORY DEVICE TEST SYSTEM
A memory device includes a controller, a multiplexer, a deserializer, a data modifier, a memory cell array and an error detector. The controller is configured...
2017/0140839 ADDRESS TRANSLATION STIMULI GENERATION FOR POST-SILICON FUNCTIONAL VALIDATION
A method for generating address translation stimuli for post-silicon functional validation is provided. The method includes determining a plurality of memory...
2017/0140838 SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASSOCIATED METHODS
An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements...
2017/0140837 SHIFT REGISTER AND THE DRIVING METHOD THEREOF, GATE DRIVING APPARATUS AND DISPLAY APPARATUS
The present invention provides a shift register, a driving method, a gate driving apparatus and a display apparatus. Said shift register comprises a pull-up...
2017/0140836 SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, SHIFT REGISTER AND DISPLAY APPARATUS
Disclosed are a shift register unit and a driving method thereof, a shift register and a display device. The shift register unit comprises: an input module...
2017/0140835 Method and Structure for Reliable Electrical Fuse Programming
A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture,...
2017/0140834 CONTROL SIGNAL GENERATION CIRCUIT AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME
A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for...
2017/0140833 ERASING MEMORY SEGMENTS IN A MEMORY BLOCK OF MEMORY CELLS USING SELECT GATE CONTROL LINE VOLTAGES
A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device...
2017/0140832 METHOD AND SYSTEM FOR IMPROVING THE RADIATION TOLERANCE OF FLOATING GATE MEMORIES
A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a...
2017/0140831 VOLTAGE GENERATION CIRCUIT WHICH IS CAPABLE OF EXECUTING HIGH-SPEED BOOST OPERATION
According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor...
2017/0140830 APPARATUSES AND METHODS FOR TRANSISTOR PROTECTION BY CHARGE SHARING
Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate...
2017/0140829 METHOD OF INITIALIZING 3D NON-VOLATILE MEMORY DEVICE
A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory...
2017/0140828 NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME
A nonvolatile memory device includes memory blocks that each include cell strings formed vertically on a substrate. The cell strings are coupled to a plurality...
2017/0140827 MEMORY DEVICE WITH VARIABLE TRIM PARAMETERS
A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or...
2017/0140826 NAND FLASH MEMORY AND PROGRAM METHOD THEREOF
A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method...
2017/0140825 SOLID STATE DRIVE DEVICES AND STORAGE SYSTEMS HAVING THE SAME
A solid state drive (SSD) device includes nonvolatile memory devices, a controller, a main power supply circuit and an auxiliary reprogram device. The...
2017/0140824 NONVOLATILE MEMORY DEVICE INCLUDING MULTI-PLANE STRUCTURE
A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through...
2017/0140823 NAND FLASH MEMORY COMPRISING A CURRENT SENSING PAGE BUFFER
Disclosed herein is a flash memory including a bit-line and a page buffer circuit. The page buffer circuit may include: a first node; a first switching circuit...
2017/0140822 SENSE AMPLIFIER CIRCUITS
A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line...
2017/0140821 System On Chip (SoC) Based On Neural Processor Or Microprocessor
System on chips (SoCs) based a microprocessor or a neural processor (e.g., brain-inspired processor) electrically coupled with electronic memory devices and/or...
2017/0140820 RRAM CELL WITH PMOS ACCESS TRANSISTOR
In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by...
2017/0140819 METHOD OF RRAM ROW FORMING
The present disclosure relates to a RRAM circuit comprising a current limiting element configured to improve forming time of RRAM cells, and an associated...
2017/0140818 VARIABLE RESISTANCE MEMORY DEVICE AND VERIFY METHOD THEREOF
A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring...
2017/0140817 MEMRISTIVE MEMORY CELL RESISTANCE SWITCH MONITORING
In the examples provided herein, a voltage driver module applies an increasing voltage to a memristive memory cell until a resistance of the cell switches to a...
2017/0140816 ACCESS SIGNAL CONDITIONING FOR MEMORY CELLS IN AN ARRAY
A memory is described having an array including two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power and a...
2017/0140815 MULTI-LEVEL RESISTIVE MEMORY STRUCTURE
A resistive memory structure comprises a resistive memory element, a resistance block electrically connected to the memory element through an electrical node,...
2017/0140814 State Dependent Sensing For Wordline Interference Correction
A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell...
2017/0140813 NONVOLATILE MEMORY DEVICE HAVNG CONNECTION UNIT FOR ALLOWING PRECHARGING OF BIT LINES IN SINGLE STEP
A nonvolatile memory device may include a cell string comprising a plurality of memory cells coupled in series; a bit line coupled to the cell string; a page...
2017/0140812 SEMICONDUCTOR DEVICE
A semiconductor device with reduced power consumption. The device includes: an n-type well region overlying the main surface of a semiconductor substrate; an...
2017/0140811 REFRESH CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING SAME
A memory device may include: at least one memory bank; and a control circuit suitable for: refreshing the at least one memory bank through a first refresh...
2017/0140810 MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME FOR CONTROLLING COLLISION BETWEEN ACCESS OPERATION AND...
A memory device includes a memory bank, a command control logic circuit, a row selection circuit, a refresh controller and a collision controller. The memory...
2017/0140809 MULTIPLE RANK HIGH BANDWIDTH MEMORY
Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory...
2017/0140808 MEMORY DEVICE HAVING LATENCY CONTROL CIRCUIT FOR CONTROLLING DATA WRITE AND READ LATENCY
A memory device may include a latency control circuit configured to control a write latency and a read latency. The memory device compensates a write latency...
2017/0140807 Circuitry for Ferroelectric FET-Based Dynamic Random Access Memory and Non-Violatile Memory
Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary...
2017/0140806 STT-MRAM CELL STRUCTURES
A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free...
2017/0140805 FAST PROGRAMMING OF MAGNETIC RANDOM ACCESS MEMORY (MRAM)
A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a...
2017/0140804 MAGNETIC JUNCTIONS HAVING ELONGATED FREE LAYERS
A magnetic junction usable in a magnetic device is described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between...
2017/0140803 CONTROL SIGNAL GENERATION CIRCUIT AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME
A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for...
2017/0140802 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes a memory device including a plurality of memory cells; and a controller suitable for determining, based on data read from the...
2017/0140801 METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND SIGNALING
Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives...
2017/0140800 VARIOUS METHODS AND APPARATUS FOR CONFIGURABLE MAPPING OF ADDRESS REGIONS ONTO ONE OR MORE AGGREGATE TARGETS
An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to...
2017/0140798 MULTI-COMMUNICATION DEVICE IN A MEMORY SYSTEM
In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed...
2017/0140797 ELECTRONIC IMAGE CREATING, IMAGE EDITING AND SIMPLIFIED AUDIO/VIDEO EDITING DEVICE, MOVIE PRODUCTION METHOD...
An audio/video editing electronic device comprising: at least visual and manual user interface means configured for allowing the interaction with said user; a...
2017/0140796 INTELLIGENT SEGMENT MARKING IN RECORDINGS
A stream of data contributions during a period is collected from a social media data source, the period spanning a broadcast of a content. The stream is...
2017/0140795 INTELLIGENT SEGMENT MARKING IN RECORDINGS
A stream of data contributions during a period is collected from a social media data source, the period spanning a broadcast of a content. The stream is...
2017/0140794 VIDEO-PROCESSING APPARATUS, VIDEO-PROCESSING SYSTEM, AND VIDEO-PROCESSING METHOD
According to the present disclosure, a master decoder acquires a generator synchronization signal for synchronization of video data based on a reference signal...
2017/0140793 METHOD FOR PROCESSING A VIDEO SCENE AND CORRESPONDING DEVICE
The present disclosure relates to a new method to make a 3D acquisition of the video scene and to replace an object of the video scene by a substitute object...
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