Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2017/0154870 Discrete Polymer in Fan-Out Packages
A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the...
2017/0154869 FLEXIBLE PACKAGES INCLUDING CHIPS
A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a...
2017/0154868 SEMICONDUCTOR PACKAGES
A semiconductor package includes a first die including first chip pads disposed in a first chip pad region, first connecting pads spaced apart from the first...
2017/0154867 METHOD FOR BONDING A HERMETIC MODULE TO AN ELECTRODE ARRAY
A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top...
2017/0154866 IMPROVED ADHESIVE BONDING COMPOSITION AND METHOD OF USE
A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one...
2017/0154865 ELECTRONIC COMPONENT MOUNTING APPARATUS
A mounting apparatus includes: a mounting tool; a supporting mechanism; a first pressurizing mechanism having a Z axis motor as a drive source for moving the...
2017/0154864 BONDING APPARATUS AND METHOD OF ESTIMATING POSITION OF LANDING POINT OF BONDING TOOL
A bonding apparatus 10 having a diagonal optical system 30, the bonding apparatus moves a capillary 24 down to a first heightwise position to calculate a...
2017/0154863 COPPER BONDING WIRE WITH ANGSTROM ( ) THICK SURFACE OXIDE LAYER
A copper wire having a diameter of 10 to 80 .mu.m is provided. The copper wire bulk material is .gtoreq.99.99 wt.-% pure copper or a copper alloy consisting of...
2017/0154862 Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a...
2017/0154861 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method...
2017/0154860 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of realizing impedance control of the...
2017/0154859 ANTENNA ASSEMBLY FOR WAFER LEVEL PACKAGING
Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a...
2017/0154858 Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices
A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes...
2017/0154857 METHOD FOR PROCESSING A WAFER AND WAFER STRUCTURE
A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a...
2017/0154856 Chip Protection Envelope and Method
In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of...
2017/0154855 POWER-MODULE SUBSTRATE UNIT AND POWER MODULE
In a power-module substrate unit, a circuit layer is structured by a plurality of small circuit layers; a ceramic substrate layer is structured by at least one...
2017/0154854 ANTI-EMI SHIELDING PACKAGE AND METHOD OF MAKING SAME
An anti-EMI shielding package includes a substrate, a component disposed on the substrate, a glue-injection layer, and a shielding metal layer covering the...
2017/0154853 METHOD FOR SINGULATING A MULTIPLICITY OF CHIPS
A method for singulating a multiplicity of chips is provided. Each chip includes a substrate, an active region arranged at least one of in or on the substrate,...
2017/0154852 FORMING METHOD OF SUPERPOSITION CHECKING MARK, MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR...
According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with...
2017/0154851 METHOD OF FORMING A DAMASCENE INTERCONNECT ON A BARRIER LAYER
A semiconductor device includes a first metal layer provided above a semiconductor substrate, an interlayer insulating film provided above the first metal...
2017/0154850 STRUCTURE FOR STACKED LOGIC PERFORMANCE IMPROVEMENT
In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection...
2017/0154849 SEMICONDUCTOR DEVICE COMPRISING POWER ELEMENTS IN JUXTAPOSITION ORDER
A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and...
2017/0154848 STANDARD-CELL LAYOUT STRUCTURE WITH HORN POWER AND SMART METAL CUT
In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a...
2017/0154847 SEMICONDUCTOR DEVICE HAVING AIR GAP STRUCTURES AND METHOD OF FABRICATING THEREOF
A device including a first conductive feature and a second conductive feature having a coplanar top surface where the conductive features are disposed a first...
2017/0154846 RAISED E-FUSE
A semiconductor device with a semiconductor-on-insulator (SOI) structure is provided including an insulating layer and a semiconductor layer formed on the...
2017/0154845 FLOATING STAIRCASE WORD LINES AND PROCESS IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate....
2017/0154844 ELECTRONIC DEVICE INCLUDING SWITCHING ELEMENT AND SEMICONDUCTOR MEMORY
An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second...
2017/0154843 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device is provided which comprises a semiconductive substrate and an interconnect on the substrate. The interconnect comprises a dielectric in...
2017/0154842 INTEGRATED CIRCUIT PACKAGE SUBSTRATE
Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a...
2017/0154841 RESIN COMPOSITION
Resin compositions containing (A) an epoxy resin, (B) a curing agent, and (C) an inorganic filler in which the content of (C) the inorganic filler is 55% by...
2017/0154840 SMD Diode Taking A Runner As Body And Manufacturing Method Thereof
A surface mount (SMD) diode taking a runner as the body and a manufacturing method thereof are described. An elongated runner groove is adopted to cure and...
2017/0154839 SEMICONDUCTOR DEVICE
A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a...
2017/0154838 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A fan-out semiconductor package includes a semiconductor chip including a body and an electrode pad disposed on the body, a metal layer disposed on the...
2017/0154837 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor module. The semiconductor module includes a package made of resin. The package contains a semiconductor element...
2017/0154836 SEMICONDUCTOR DEVICE
In order to restrict cracking or the like in a connection member such as solder, provided is a semiconductor device including a first component; a second...
2017/0154834 SEMICONDUCTOR MODULE THAT HAVE MULTIPLE PATHS FOR HEAT DISSIPATION
A semiconductor module includes a substrate, first and second wirings on the substrate, a semiconductor package disposed on the first wiring and having a pair...
2017/0154833 SEMICONDUCTOR DEVICE
A semiconductor device capable of carrying out temperature detection appropriately by a temperature sensor is provided. In a semiconductor device disclosed...
2017/0154832 SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME
A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an...
2017/0154831 Electronic Component and Method
In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least...
2017/0154830 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device is provided. The method includes the following operations. (a) A substrate is patterned. (b) A polymer layer...
2017/0154829 ETCHING METHOD AND ETCHANT
An etching method for detecting crystal defects, the method includes providing a substrate with an etchant containing hydrogen fluoride, nitric acid, hydrogen...
2017/0154828 ADAPTIVE TCB BY DATA FEED FORWARD
A method and machine-readable medium including non-transitory program instructions that when executed by a processor cause the processor to perform a method...
2017/0154827 WELL IMPLANTATION PROCESS FOR FINFET DEVICE
A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate...
2017/0154826 METHOD FOR FORMING SPACERS FOR A TRANSITOR GATE
A method for forming spacers of a gate of a field-effect transistor is provided, including at least one step of forming a protective layer covering the gate;...
2017/0154825 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR REPLACEMENT GATE HIGH-K METAL GATE DEVICES WITH WORK FUNCTION ADJUSTMENTS
An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first...
2017/0154824 Nano Wire Structure and Method for Fabricating the Same
A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning...
2017/0154823 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon;...
2017/0154822 SPACER STRUCTURE AND MANUFACTURING METHOD THEREOF
A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are...
2017/0154821 SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR
A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second...
2017/0154820 FETS AND METHODS OF FORMING FETS
An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.