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Patent # Description
2017/0154819 SYSTEMS AND METHODS FOR CONTROLLING RELEASE OF TRANSFERABLE SEMICONDUCTOR STRUCTURES
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a...
2017/0154818 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main...
2017/0154817 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the...
2017/0154816 AMORPHOUS METAL INTERCONNECTIONS BY SUBTRACTIVE ETCH
A method of fabricating amorphous metal interconnections includes forming an amorphous metal layer over a base insulating layer on a semiconductor device using...
2017/0154815 HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form...
2017/0154814 INTERCONNECT STRUCTURE AND METHODS OF MAKING SAME
A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the...
2017/0154813 SELF-ORGANIZING BARRIER LAYER DISPOSED BETWEEN A METALLIZATION LAYER AND A SEMICONDUCTOR REGION
According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a...
2017/0154812 ENHANCED VIA FILL MATERIAL AND PROCESSING FOR DUAL DAMSCENE INTEGRATION
A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the...
2017/0154811 Wafer Level Chip Scale Package Interconnects and Methods of Manufacture Thereof
A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an...
2017/0154810 METHOD FOR MAKING PATTERNS BY SELF-ASSEMBLY OF BLOCK COPOLYMERS
A method for making patterns includes forming on a substrate surface a first mask delimiting at least two areas to be metallised; forming an assembly guide...
2017/0154809 METHODS OF FORMING FINE PATTERNS INCLUDING PAD PORTION AND LINE PORTION
A method of forming fine patterns includes forming a partition on a base layer. The partition includes a partition block, a first open region provided to face...
2017/0154808 Substrates with Buried Isolation Layers and Methods of Formation Thereof
A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the...
2017/0154807 Vertical Structure and Method of Forming Semiconductor Device
According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a...
2017/0154806 SELECTIVE DEPOSITION OF ALUMINUM AND NITROGEN CONTAINING MATERIAL
Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric...
2017/0154805 SEMICONDUCTOR DEVICE INCLUDING AIR SPACER
A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second...
2017/0154804 CONTROL OF THE INCIDENCE ANGLE OF AN ION BEAM ON A SUBSTRATE
One system includes a chamber, a chuck assembly, and an ion source. The chuck assembly includes a substrate support and a precession assembly with a center...
2017/0154803 NON-CONTACT WAFER TRANSPORT DEVICE
A non-contact wafer transport device for transporting a wafer to be transported includes a base, a moving arm, a tube disposed in the moving arm and a negative...
2017/0154802 WAFER LAMINATE AND MAKING METHOD
A wafer laminate has an adhesive layer (3) sandwiched between a transparent substrate (1) and a water (2), with a circuit-forming surface of the wafer facing...
2017/0154801 WAFER PROCESSING LAMINATE AND METHOD FOR PROCESSING WAFER
A wafer processing laminate including support, temporary adhesive material layer laminated on the support, and wafer stacked on temporary adhesive material...
2017/0154800 WAFER HANDLER AND METHODS OF MANUFACTURE
A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed...
2017/0154799 SUBSTRATE TRANSFER CHAMBER AND CONTAINER CONNECTING MECHANISM
A substrate transfer chamber for unloading the substrates from the containers includes a housing-shaped main body and a plurality of container connecting...
2017/0154798 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device, includes: a preparation step, a flow step, and a processing step. The preparation step prepares an etching...
2017/0154797 METHOD AND APPARATUS FOR POST EXPOSURE PROCESSING OF PHOTORESIST WAFERS
Embodiments described herein relate to methods and apparatus for performing immersion field guided post exposure bake processes. Embodiments of apparatus...
2017/0154796 SUBSTRATE TREATMENT APPARATUS, AND SUBSTRATE TREATMENT METHOD
The inventive substrate treatment apparatus includes: a rotative treatment control unit which controls a first chemical liquid supplying unit and a second...
2017/0154795 LIQUID KNIFE CLEANING DEVICE
A liquid knife cleaning device is provided, and it includes a splash shield; a liquid knife, which is located under the splash shield; an oblique baffle, which...
2017/0154794 Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices
Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device...
2017/0154793 CHIP PACKAGE METHOD AND CHIP PACKAGE STRUCTURE
A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a...
2017/0154792 METHOD OF MOUNTING ELECTRONIC DEVICE AND UNDER-FILL FILM USED THERETO
A method of mounting an electronic device includes: preparing a printed circuit board including a base substrate, connection pads disposed on the base...
2017/0154791 DESMEAR TREATMENT DEVICE AND DESMEAR TREATMENT METHOD
The present invention has as its object the provision of a desmear treatment device and a desmear treatment method capable of reliably performing a desmear...
2017/0154790 SAM ASSISTED SELECTIVE E-LESS PLATING ON PACKAGING MATERIALS
A method including activating an area of a polymer layer on a substrate with electromagnetic radiation; modifying the activated area; forming a self-assembled...
2017/0154789 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
To provide a highly reliable semiconductor device using an oxide semiconductor. The semiconductor device includes a first electrode layer; a second electrode...
2017/0154788 SiGe FINS FORMED ON A SUBSTRATE
A semiconductor structure formed based on selectively forming a silicon--germanium (SiGe) layer on a substrate; forming at least one fin with a first width...
2017/0154787 CMP POLISHING LIQUID AND POLISHING METHOD
An embodiment of the present invention relates to a CMP polishing liquid used for polishing a polishing target surface having at least a cobalt-containing...
2017/0154786 HEAT TREATMENT APPARATUS, HEAT TREATMENT METHOD, AND PROGRAM
A heat treatment system includes a heating unit that heats an inside of a processing chamber that accommodates a plurality of workpieces; a pressure adjusting...
2017/0154785 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS
According to one embodiment, a method for manufacturing a semiconductor device includes the following processes. Second layers and first layers are alternately...
2017/0154784 METHOD OF ETCHING
A method of etching an insulation layer on an object to be processed in a process chamber in which an upper electrode and a lower electrode are placed facing...
2017/0154783 EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING
A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth...
2017/0154782 COMPOSITION FOR FILM FORMATION, FILM, PRODUCTION METHOD OF PATTERNED SUBSTRATE, AND COMPOUND
A composition comprises a compound comprising a partial structure represented by formula (1) and comprising an intermolecular bond-forming group; and a...
2017/0154781 METHOD FOR ETCHING HIGH-K DIELECTRIC USING PULSED BIAS POWER
A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a...
2017/0154780 SUBSTRATE PROCESSING METHOD AND APPARATUS THEREOF
The invention relates to a substrate processing method and relevant apparatus. The method includes: placing the substrate into a reactor consist by several...
2017/0154779 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and...
2017/0154778 SILANE AND BORANE TREATMENTS FOR TITANIUM CARBIDE FILMS
Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film...
2017/0154777 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
A semiconductor device manufacturing method of present application includes a catalytic step of depositing catalytic metal on a surface of a semiconductor...
2017/0154776 3D MATERIAL MODIFICATION FOR ADVANCED PROCESSING
Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques....
2017/0154775 METHOD FOR FORMING A STRAINED SEMICONDUCTOR LAYER INCLUDING REPLACING AN ETCHABLE MATERIAL FORMED UNDER THE...
A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an...
2017/0154774 IMPROVING CHANNEL STRAIN AND CONTROLLING LATERAL EPITAXIAL GROWTH OF THE SOURCE AND DRAIN IN FINFET DEVICES
A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side....
2017/0154773 METHOD FOR MANUFACTURING TFT SUBSTRATE AND TFT SUBSTRATE MANUFACTURED THEREOF
The invention provides a method for manufacturing a TFT substrate and a TFT substrate manufactured thereof. In the above TFT substrate, the low temperature...
2017/0154772 Semiconductor Devices and Methods of Manufacture Thereof
A method includes depositing an insulating layer over a substrate, the substrate including a first semiconductor material. The method also includes forming an...
2017/0154771 SELECTIVE AREA GROWTH OF SEMICONDUCTORS USING PATTERNED SOL-GEL MATERIALS
Systems and methods for growing semiconductor materials on substrates by using patterned sol-gel materials are provided. According to a first aspect of the...
2017/0154770 METHODS OF FORMING SILICON GERMANIUM TIN FILMS AND STRUCTURES AND DEVICES INCLUDING THE FILMS
Methods of forming silicon germanium tin (SiGe.sub.xGe.sub.1-xSn.sub.y) films are disclosed. Exemplary methods include growing films including silicon,...
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