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Patent # Description
2017/0154011 IP MULTICAST ADDRESS GENERATION AND SUBSCRIPTION
A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN) begins, when processing a slice...
2017/0154010 SYSTEMS AND METHODS FOR TRANSMITTING AN ACCESS REQUEST VIA A FLEXIBLE REGISTER ACCESS BUS
Some embodiments described herein provide a method for transmitting an access request via a flexible register access bus. An access request may be received to...
2017/0154009 METHOD FOR INTERFACE INITIALIZATION USING BUS TURN-AROUND
An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a...
2017/0154008 Dynamic Re-Allocation of Computer Bus Lanes
The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted....
2017/0154007 LOGIC-BASED DECODER FOR CROSSTALK-HARNESSED SIGNALING
A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than...
2017/0154006 VEHICLE ENTERTAINMENT ASSEMBLIES AND SYSTEMS
Methods and systems are disclosed relating to in-vehicle entertainment, information presentation, and/or processing. Aspects of multimedia in-vehicle...
2017/0154005 System and Method for Managing Workloads and Hot-Swapping a Co-Processor of an Information Handling System
An information handling system includes a host processing complex and a wireless management system. The host processing complex instantiates a hosted...
2017/0154004 INFORMATION PROCESSING APPARATUS AND METHOD FOR GENERATING COUPLING INFORMATION
A processing apparatus includes a memory, and a processor coupled to the memory and configured to acquire first data that indicates correspondence relationship...
2017/0154003 MEMORY CARD
Provided is a memory card, which includes two pairs of opposite edges, first row terminals arranged adjacent to an insertion-side edge of the memory card, and...
2017/0154002 INTEGRATED CIRCUIT AND OPERATION METHOD OF SERIALIZER/DESERIALIZER PHYSICAL LAYER CIRCUIT THEREOF
An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration...
2017/0154001 SUPER HUB SYSTEM AND THE METHOD THEREOF
A system includes at least two ports (22, 24, 26) connected to particular electronic products. The system is able to intelligently detect the master/slave...
2017/0154000 Dynamic Re-Allocation of Computer Bus Lanes
The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication...
2017/0153999 RECORDING MEDIUM, ADAPTER, AND INFORMATION PROCESSING APPARATUS
A recording medium to be used by being connected to a digital device includes a local bus, a plurality of recording units, an information storage unit, and a...
2017/0153998 SYSTEM, METHOD, AND RECORDING MEDIUM FOR TOPOLOGY-AWARE PARALLEL REDUCTION IN AN ACCELERATOR
A topology-aware parallel reduction method, system, and recording medium including a partitioning device configured to partition data in each accelerator of a...
2017/0153997 BUS SYSTEM
A bus system is provided. The bus system includes a master device, a bus and a plurality of slave devices. The slave devices and the master device are...
2017/0153996 NON-LINEAR TRANSMIT BIASING FOR A SERIAL BUS TRANSMITTER
Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to...
2017/0153995 DATA TRANSFER DEVICE
A data transfer device includes a shifter block that generates first and second input signals and first and second output signals, an input/output control...
2017/0153994 MASS STORAGE REGION WITH RAM-DISK ACCESS AND DMA ACCESS
An apparatus is described that includes a non volatile memory interface to couple to a non volatile random access memory comprising a mass storage region. The...
2017/0153992 SMART DEVICE AND METHOD OF OPERATING THE SAME
A smart device and a method of operating the same are provided. The smart device includes a processor, and a sensor configured to detect movement of the smart...
2017/0153991 CONFIGURABLE PROCESSOR INTERRUPTS
Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request,...
2017/0153990 Integrated Circuit with a Serial Interface
An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated...
2017/0153989 Dynamic Allocation of Computer Bus Lanes
The embodiments relate to dynamically allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted....
2017/0153988 INTEGRATED CIRCUIT SECURITY
An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data...
2017/0153987 IMPLICIT SHARING IN STORAGE MANAGEMENT
A physical address of a page may be identified. A first process that implements copy-on-read techniques for the page may be detected. A determination may be...
2017/0153986 CACHE LONGEVITY DETECTION AND REFRESH
A web server cache performs verification of cached computational results by storing a computed function result as a cached value in a cache, and upon receiving...
2017/0153985 METHOD TO EFFICIENTLY IMPLEMENT SYNCHRONIZATION USING SOFTWARE MANAGED ADDRESS TRANSLATION
Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in...
2017/0153984 APPARATUS AND METHOD FOR ACCELERATING OPERATIONS IN A PROCESSOR WHICH USES SHARED VIRTUAL MEMORY
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an...
2017/0153983 SUPERVISORY MEMORY MANAGEMENT UNIT
A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU)...
2017/0153982 INVALIDATION OF TRANSLATION LOOK-ASIDE BUFFER ENTRIES BY A GUEST OPERATING SYSTEM
Embodiments disclose techniques for enabling a guest operating system (OS) to directly invalidate entries in a translation lookaside buffer (TLB). In one...
2017/0153981 Using Shared Virtual Memory Resources for Performing Memory-Mapping
Functionality is described herein for memory-mapping an information unit (such as a file) into virtual memory by associating shared virtual memory resources...
2017/0153980 ANONYMIZED NETWORK ADDRESSING IN CONTENT DELIVERY NETWORKS
Systems, methods, apparatuses, and software for a content delivery network that caches content for delivery to end user devices is presented. In one example, a...
2017/0153979 DYNAMIC RESULT SET CACHING WITH A DATABASE ACCELERATOR
According to one embodiment of the present invention, a system for processing a database query stores one or more result sets for one or more first database...
2017/0153978 OPTIMIZED CACHING OF SLICES BY A DS PROCESSING UNIT
A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational...
2017/0153977 DATA CACHING
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods...
2017/0153976 ASYNCHRONOUS CLEANUP AFTER A PEER-TO-PEER REMOTE COPY (PPRC) TERMINATE RELATIONSHIP OPERATION
For asynchronous cleanup after a peer-to-peer remote copy (PPRC) terminate relationship operation in a computing storage environment by a processor device,...
2017/0153975 APPARATUS AND METHOD FOR HANDLING ATOMIC UPDATE OPERATIONS
An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry,...
2017/0153974 DUAL SPACE STORAGE MANAGEMENT SYSTEM AND DATA READ/WRITE METHOD
A computer system includes an addressing assembly, connected respectively to high bits of a memory address line of a processor and high bits of a word address...
2017/0153973 FACILITATING EFFICIENT GARBAGE COLLECTION BY DYNAMICALLY COARSENING AN APPEND-ONLY LOCK-FREE TRIE
The disclosed embodiments provide a remembered set implementation for use during an incremental garbage collection, wherein the implementation includes a trie...
2017/0153972 Relocating A Virtual Address In A Persistent Memory
Some examples described herein relate to relocating a virtual address in a persistent memory. An example includes determining whether a base address of a...
2017/0153971 GLOBALIZATION TESTING MANAGEMENT SERVICE CONFIGURATION
Disclosed aspects may include examining a set of product development data of a product development environment. In response to the examining, a set of...
2017/0153970 GLOBALIZATION TESTING MANAGEMENT USING A SET OF GLOBALIZATION TESTING OPERATIONS
Disclosed aspects may include collecting a set of globalization data. The set of globalization data may relate to a set of globalization parameters. Based on...
2017/0153969 SYSTEM AND METHOD FOR EXECUTING INTEGRATION TESTS IN MULTIUSER ENVIRONMENT
System and method for executing integration tests for testing software code are disclosed. The system comprises multi-user integrated test framework to...
2017/0153968 DATABASE CONFIGURATION CHECK
A system includes determination of a plurality of database configuration checks, execution of the plurality of database configuration checks against database...
2017/0153967 USING MODEL-BASED DIAGNOSIS TO IMPROVE SOFTWARE TESTING
An artificial intelligence based method for improving a software testing process, according to which upon finding a bug, a set of candidate diagnoses is...
2017/0153966 STREAMS: INTELLIGENT OPERATOR SUBSET FOR DEBUG
Techniques are disclosed for identifying a minimal operator subsets in a distributed streams application for debugging purposes. A debugging tool receives a...
2017/0153965 LISTING OPTIMAL MACHINE INSTANCES
A method for listing optimal machine instances in a computing environment based on user context is provided. The method includes receiving a task request based...
2017/0153964 MONITORING AND RESPONDING TO OPERATIONAL CONDITIONS OF A LOGICAL PARTITION FROM A SEPARATE LOGICAL PARTITION
Communicating with a logical partition of a computing system based on a separate logical partition in which each of one or more computing systems includes a...
2017/0153963 Method and System for Pre-Deployment Performance Estimation of Input-Output Intensive Workloads
A method and system is provided for pre-deployment performance estimation of input-output intensive workloads. Particularly, the present application provides a...
2017/0153962 MONITORING THE PERFORMANCE OF THREADED APPLICATIONS
An ability to monitor the performance of a threaded application is provided. A thread that is executing is detected, wherein the thread is spawned by a...
2017/0153961 SOLID STATE DISK
A solid state disk, including a main body, a processing unit, a display screen and a transmit port. The main body has a substrate and a shell portion covering...
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