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Patent # Description
2017/0162572 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main...
2017/0162570 Complementary Transistor Pair Comprising Field Effect Transistor Having Metal Oxide Channel Layer
A complementary transistor pair with an n-type enhancement-mode field effect transistor and a p-type field effect transistor is disclosed. The n-type...
2017/0162569 GATE-ALL-AROUND FIN DEVICE
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a...
2017/0162568 SEMICONDUCTOR DEVICE
A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an...
2017/0162567 SELF HEATING REDUCTION FOR ANALOG RADIO FREQUENCY (RF) DEVICE
A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a...
2017/0162566 SEMICONDUCTOR DEVICE
A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the...
2017/0162565 STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set...
2017/0162564 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second ...
2017/0162563 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a...
2017/0162562 SEMICONDUCTOR DEVICE
An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type...
2017/0162561 Reverse Bipolar Junction Transistor Integrated Circuit
A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base...
2017/0162560 SEMICONDUCTOR DEVICE
A semiconductor device includes a switching device region including an active region having a first conductivity-type emitter region formed on an upper surface...
2017/0162559 INTEGRATED VERTICAL SHARP TRANSISTOR AND FABRICATION METHOD THEREOF
The present invention relates to vertical integrated, quantized FET with sharp drain and BJT with sharp emitter implemented in one nano-BiCMOS process, using...
2017/0162558 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a...
2017/0162557 TRENCH BASED CHARGE PUMP DEVICE
A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate...
2017/0162556 SEMICONDUCTOR ASSEMBLY HAVING ANTI-WARPING CONTROLLER AND VERTICAL CONNECTING ELEMENT IN STIFFENER
A semiconductor assembly includes an anti-warping controller, a semiconductor device, a balance layer and a first routing circuitry positioned within a through...
2017/0162555 SOLDER COMPOSITION AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Solder compositions for semiconductor fabrication are provided that include silver (Ag) of 3.0 wt. % to 4.0 wt. %, copper (Cu) of 0.75 wt. % to 1.0 wt. %,...
2017/0162554 SELF-ALIGNED THREE DIMENSIONAL CHIP STACK AND METHOD FOR MAKING THE SAME
Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips...
2017/0162553 LED DISPLAY WITH WAVELENGTH CONVERSION LAYER
A display and method of manufacture are described. The display may include a substrate including an array of pixels with each pixel including multiple...
2017/0162552 LASER LIFT-OFF ON ISOLATED III-NITRIDE LIGHT ISLANDS FOR INTER-SUBSTRATE LED TRANSFER
A laser liftoff process is provided. A device layer can be provided on a transfer substrate. Channels can be formed through the device layer such that devices...
2017/0162551 Semiconductor Device and Method of Manufactures
A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through...
2017/0162550 Interconnect Structures For Assembly Of Semiconductor Structures Including At Least One Integrated Circuit...
A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a...
2017/0162549 ELECTRONIC ASSEMBLIES
The electronic assemblies described in this specification are characterized by a non-planar low-temperature co-fired ceramic substrate on which an electronic...
2017/0162548 LIGHT EMITTING DEVICE AND LIGHTING SYSTEM HAVING THE SAME
The present invention provides a light emitting device comprising a first light emitting portion that emits white light at a color temperature of 6000K or more...
2017/0162547 Solid State Light Fixtures Suitable for High Temperature Operation Having Separate Blue-Shifted-Yellow/Green...
Solid state light fixtures include a plurality of blue-shifted-yellow/green light emitting diode ("LED") packages and a plurality of blue-shifted-red LED...
2017/0162546 SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit ("IC") package substrate capable of...
2017/0162545 STACKED SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
A stacked semiconductor device includes a plurality of semiconductor dies and a plurality of thermal-mechanical bumps. The semiconductor dies are stacked in a...
2017/0162544 SEMICONDUCTOR DEVICE
There is provided a semiconductor device, enhanced with process capability and reliability by way of flow control of an adhesive material to fix semiconductor...
2017/0162543 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a first semiconductor chip adjacent a second semiconductor chip. The first semiconductor chip includes a first surface and a...
2017/0162542 Packages with Thermal Management Features for Reduced Thermal Crosstalk and Methods of Forming Same
An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour...
2017/0162541 Semiconductor Devices and Methods of Manufacture Thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of...
2017/0162540 WAFER-LEVEL CHIP-SCALE PACKAGE WITH REDISTRIBUTION LAYER
A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The...
2017/0162539 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding...
2017/0162538 METHOD FOR APPLYING A BONDING LAYER
A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of...
2017/0162537 ADHESIVE BONDING COMPOSITION AND WAFER-TO-WAFER BONDED ASSEMBLY PREPARED FROM THE SAME
A polymerizable composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and a...
2017/0162536 NANOWIRES FOR PILLAR INTERCONNECTS
An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may...
2017/0162535 TRANSIENT INTERFACE GRADIENT BONDING FOR METAL BONDS
A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without...
2017/0162534 CHIP ATTACH FRAME
A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges...
2017/0162533 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element...
2017/0162532 Edge Interconnect Packaging of Integrated Circuits for Power Systems
Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more...
2017/0162531 COMPOSITION FOR ANISOTROPIC CONDUCTIVE FILM, ANISOTROPIC CONDUCTIVE FILM, AND CONNECTION STRUCTURE USING THE SAME
An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same, the anisotropic...
2017/0162530 Packaged IC with Solderable Sidewalls
A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls...
2017/0162529 ANISOTROPIC CONDUCTIVE FILM AND CONNECTION STRUCTURE
In order to easily inspect a dispersion state of conductive particles in such an anisotropic conductive film that the conductive particles are dispersed even...
2017/0162528 Semiconductor Device
A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor...
2017/0162527 ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME
An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first...
2017/0162526 METHOD TO IMPROVE CMP SCRATCH RESISTANCE FOR NON PLANAR SURFACES
A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate,...
2017/0162525 HIGH FREQUENCY SEMICONDUCTOR AMPLIFIER
A high frequency semiconductor amplifier includes an input circuit, a first semiconductor element, first bonding wires, an interstage circuit, second bonding...
2017/0162524 Antennas and Waveguides in InFO Structures
A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with...
2017/0162523 PACKAGE SUBSTRATE
A package substrate is disclosed. The package substrate includes a molding layer, a redistribution structure, and a build-up structure. The redistribution...
2017/0162522 STRESS RELIEF IN SEMICONDUCTOR WAFERS
Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an...
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