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Patent # Description
2017/0162521 WAFER PROCESSING METHOD
Disclosed herein is a wafer processing method including a stacked member removing step of applying a laser beam having an absorption wavelength to a stacked...
2017/0162520 LEAD FRAME, ELECTRONIC COMPONENT DEVICE, AND METHODS OF MANUFACTURING THEM
A lead frame includes a terminal part having a first side surface formed in a concave curve shape on a lower side from an upper end of the terminal part, and a...
2017/0162519 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a method of...
2017/0162518 Protection Structure for Semiconductor Device Package
A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein...
2017/0162517 PACKAGING FOR HIGH SPEED CHIP TO CHIP COMMUNICATION
Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip...
2017/0162516 SEMICONDUCTOR PACKAGES INCLUDING SIDE SHIELDING PARTS
A method of fabricating a semiconductor package is provided. The method includes providing a package substrate strip including chip mounting regions, bridge...
2017/0162515 SEMICONDUCTOR PACKAGES INCLUDING A SHIELDING PART AND METHODS FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor package and the semiconductor package are provided. The method for manufacturing a semiconductor package may include...
2017/0162514 SEMICONDUCTOR PACKAGE WITH ANTENNA
A semiconductor package includes a substrate, a plurality of pin pads, a radio frequency (RF) pad, a semiconductor component, at least one surface mount device...
2017/0162512 Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition
A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a...
2017/0162511 DIELECTRIC/METAL BARRIER INTEGRATION TO PREVENT COPPER DIFFUSION
An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a...
2017/0162510 SEMICONDUCTOR DEVICE WITH EMBEDDED SEMICONDUCTOR DIE AND SUBSTRATE-TO-SUBSTRATE INTERCONNECTS
A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top...
2017/0162509 HIGH DENSITY INTERCONNECT DEVICE AND METHOD
Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are...
2017/0162508 STRAIN ENGINEERING DEVICES USING PARTIAL DEPTH FILMS IN THROUGH-SUBSTRATE VIAS
Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer...
2017/0162507 Semiconductor Structures For Assembly In Multi-Layer Semiconductor Devices Including At Least One Semiconductor...
A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second...
2017/0162506 Interconnect Structure and Method of Forming Same
An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a...
2017/0162505 SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad...
2017/0162504 Metal Line Structure and Method
A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface,...
2017/0162503 MOS ANTIFUSE WITH VOID-ACCELERATED BREAKDOWN
A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at...
2017/0162502 Semiconductor Devices and Methods of Forming Same
Embodiments of the present disclosure include a semiconductor device and methods of forming the same. A representative embodiment includes a method of forming...
2017/0162501 CRACK STOP LAYER IN INTER METAL LAYERS
Devices and methods for forming a device are presented. The method includes providing a substrate prepared with interlevel dielectric (ILD) layers having...
2017/0162500 SEMICONDUCTOR DEVICE
A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the...
2017/0162499 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER...
A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy...
2017/0162498 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER...
A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are...
2017/0162497 METAL VIA STRUCTURE
A filled metal via having an adhesive layer configured on bottom is disclosed. The adhesive layer enhances bonding force between the filled metal via and a...
2017/0162496 TRENCH SILICIDE WITH SELF-ALIGNED CONTACT VIAS
A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a...
2017/0162495 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED PAD ON LAYERED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the...
2017/0162494 METHOD FOR FABRICATING PACKAGE STRUCTURE
A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric...
2017/0162493 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor...
2017/0162492 IC Carrier of Semiconductor Package and Manufacturing Method Thereof
The present invention discloses an IC Carrier of a semiconductor package and its manufacturing method. The IC Carrier of the semiconductor package includes a...
2017/0162491 Chip-size, double side connection package and method for manufacturing the same
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post...
2017/0162490 SEMICONDUCTOR DEVICE, PACKAGE, AND VEHICLE
A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed...
2017/0162489 Flat No-Lead Packages with Electroplated Edges
A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet...
2017/0162488 PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE
Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a...
2017/0162487 CHIP ON FILM PACKAGE
A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first...
2017/0162486 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of...
2017/0162485 SEMICONDUCTOR DEVICE
[Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes:...
2017/0162484 THERMALLY CONDUCTIVE SHEET AND SEMICONDUCTOR DEVICE
A thermally conductive sheet of the present invention includes a thermosetting resin (A), and an inorganic filler material (B) which is dispersed in the...
2017/0162483 ELECTRONIC PACKAGES FOR FLIP CHIP DEVICES
Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an...
2017/0162482 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element and an electrically conductive member. The semiconductor element is configured to allow an electric...
2017/0162481 SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE
Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of...
2017/0162480 SEMICONDUCTOR DEVICE
A semiconductor device includes a resin package, a semiconductor chip sealed in the package and having first and second pads on a front surface. An island of...
2017/0162479 SEMICONDUCTOR DEVICE WITH FRAME HAVING ARMS AND RELATED METHODS
A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending...
2017/0162478 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
The present disclosure provides a semiconductor device and a semiconductor device manufacturing method that may prevent positional displacement of an...
2017/0162477 LEAD FRAME AND LIGHT EMITTING DIODE PACKAGE HAVING THE SAME
A lead frame for an LED package includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the...
2017/0162476 Connector block with two sorts of through connections, and electronic device comprising a connector block
An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip...
2017/0162475 HEAT EXCHANGER METHODS, APPARATUSES AND SYSTEMS WITH A MANIFOLD STRUCTURE
Methods, apparatuses and systems associated with a heat exchanger for cooling an IC package are disclosed herein. In embodiments, a heat exchanger may include...
2017/0162474 COOLING MODULE AND ELECTRONIC DEVICE
The cooling module includes a heat sink for cooling a power component of an ultrasonic source and a resonance tube arranged between the ultrasonic source and...
2017/0162473 SYSTEMS AND METHODS FOR THERMAL CONTROL OF INTEGRATED CIRCUITS
A system includes a carrier defining a plurality of channels. The system includes an integrated circuit (IC) die having a first side and having a second side...
2017/0162472 Power Semiconductor Module and Manufacturing Method of Power Semiconductor Module
An object of the present invention is to provide a power semiconductor module that can secure a satisfactory cooling without expanding the size of a case...
2017/0162471 PHASE CHANGING ON-CHIP THERMAL HEAT SINK
A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the...
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