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Patent # Description
2017/0162470 Clamping Assembly Having A Pressure Element
A clamping assembly includes a configuration of mechanically clamped components disposed one on top of the other to form a stack. A clamping device generates a...
2017/0162469 SILICON CARBIDE COMPLEX, METHOD FOR MANUFACTURING SAME, AND HEAT DISSIPATION COMPONENT USING SAME
[Problem] To inexpensively provide a heat dissipating component that has thermal conductivity, as well as a low specific gravity, and a coefficient of thermal...
2017/0162468 POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Disclosed relates to a power module package and a method for manufacturing the same. The power module package includes a lower substrate on which a pattern is...
2017/0162467 AN ELECTRONIC DEVICE COMPONENT WITH AN INTEGRAL DIAMOND HEAT SPREADER
An electronic device component comprising: a support frame comprising a top surface, a bottom surface, and an opening extending between the top surface and...
2017/0162466 INTELLIGENT POWER MODULE, ELECTRIC VEHICLE, AND HYBRID CAR
An intelligent power module includes at least one power semiconductor module including a semiconductor device, and a sealing body sealing an outer periphery of...
2017/0162465 INVERTER
An inverter includes: an inverter circuit including: a power semiconductor module; and an inverter circuit module including a passive component; a cooler...
2017/0162464 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor chip formed using a silicon carbide and having electrodes on a first surface and a second surface opposite to...
2017/0162463 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed...
2017/0162462 SEMICONDUCTOR DEVICE
A semiconductor device includes: a sealing body that seals a first semiconductor element and a second semiconductor element; first heat-radiating members...
2017/0162461 Semiconductor Device and Method of Manufacturing Thereof
A semiconductor device is provided. The semiconductor device includes a first semiconductor component having a semiconductor substrate, and a barrier layer...
2017/0162460 Semiconductor substrate-on-semiconductor substrate package and method of manufacturing the same
A semiconductor assembly includes a first semiconductor substrate having a first main surface and a second main surface and a second semiconductor substrate...
2017/0162459 Apparatus and Method for Ion Implantation
An apparatus and a method for implanting ions are disclosed. In an embodiment, the apparatus includes a receptacle configured to support the wafer, a source of...
2017/0162458 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes: digging first and second trenches at the top surface of a plate-like base-body portion; forming an...
2017/0162457 AUTOMATIC SAMPLING OF HOT PHOSPHORIC ACID FOR THE DETERMINATION OF CHEMICAL ELEMENT CONCENTRATIONS AND CONTROL...
Systems and methods for automatic sampling of a sample for the determination of chemical element concentrations and control of semiconductor processes are...
2017/0162456 Systems and methods of characterizing process-induced wafer shape for process control using CGS interferometry
Systems and methods of characterizing wafer shape using coherent gradient sensing (CGS) interferometry are disclosed. The method includes measuring at least...
2017/0162455 METHOD AND STRUCTURE FOR FLIP-CHIP PACKAGE RELIABILITY MONITORING USING CAPACITIVE SENSORS GROUPS
Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time...
2017/0162454 SYSTEMS AND METHODS FOR INTERCONNECT SIMULATION AND CHARACTERIZATION
Exemplary systems and methods allow for precise formation and subsequent characterization of electrical interconnects, for example solder joints associated...
2017/0162453 TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S)
Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In...
2017/0162452 SEMICONDUCTOR NANOWIRE DEVICE AND FABRICATION METHOD THEREOF
A method for fabricating a semiconductor nanowire device includes forming a base including a plurality of PMOS regions, forming a plurality of first openings...
2017/0162451 METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of...
2017/0162450 SEMICONDUCTOR PROCESS
A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At...
2017/0162449 METHOD OF FORMING SEMICONDUCTOR STRUCTURE
A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each...
2017/0162448 METAL REFLOW FOR MIDDLE OF LINE CONTACTS
A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD)...
2017/0162447 TECHNIQUES FOR FORMING GE/SIGE-CHANNEL AND III-V-CHANNEL TRANSISTORS ON THE SAME DIE
Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of...
2017/0162446 MULTIPLE GATE LENGTH VERTICAL FIELD-EFFECT-TRANSISTORS
Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a...
2017/0162445 SELF HEATING REDUCTION FOR ANALOG RADIO FREQUENCY (RF) DEVICE
A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a...
2017/0162444 CONTACT RESISTANCE REDUCTION FOR ADVANCED TECHNOLOGY NODES
A source/drain contact includes a first portion arranged on a substrate and extending between a first gate and a second gate; a second portion arranged on the...
2017/0162443 MIDDLE OF THE LINE SUBTRACTIVE SELF-ALIGNED CONTACTS
A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching...
2017/0162442 SEMICONDUCTOR DEVICE
A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels....
2017/0162441 WAFER PROCESSING METHOD
A wafer is divided into a plurality of individual devices along a plurality of division lines, the wafer being composed of a substrate and a functional layer...
2017/0162440 LOW CAPACITANCE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of...
2017/0162439 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes: forming a resist separation layer on a first main surface of a SiC substrate; applying a resist...
2017/0162438 GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts...
2017/0162437 MIDDLE OF THE LINE SUBTRACTIVE SELF-ALIGNED CONTACTS
A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching...
2017/0162436 NANOWIRES FOR PILLAR INTERCONNECTS
An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may...
2017/0162435 METHOD OF SPACER PATTERNING TO FORM A TARGET INTEGRATED CIRCUIT PATTERN
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the...
2017/0162434 WIRING STRUCTURE AND METHOD OF FORMING A WIRING STRUCTURE
A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure...
2017/0162433 METHOD FOR MANUFACTURING A DEVICE ISOLATION STRUCTURE
A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that...
2017/0162432 Method and Apparatus for Semiconductor Planarization
A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode...
2017/0162431 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a...
2017/0162430 METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AIR GAPS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS
Methods for producing integrated circuits and integrated circuits produced by such methods are provided. In an exemplary embodiment, a method for producing an...
2017/0162429 SEMICONDUCTOR DEVICES WITH BACK SURFACE ISOLATION
Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective...
2017/0162428 ROOM-TEMPERATURE BONDING APPARATUS
A room-temperature bonding apparatus includes a bonding chamber, an upper-side stage mechanism to support an upper-side wafer to be movable in an upper and...
2017/0162427 SPIN CHUCK WITH IN SITU CLEANING CAPABILITY
In a method and apparatus for processing wafer-shaped articles, a spin chuck is positioned inside a process chamber. The spin chuck is configured to hold a...
2017/0162426 SPIN CHUCK WITH GAS LEAKAGE PREVENTION
An apparatus for processing wafer-shaped articles, comprises a process chamber, and a spin chuck positioned inside the process chamber. The spin chuck is...
2017/0162425 SUSCEPTOR AND METHOD FOR MANUFACTURING SAME
Provided are a susceptor that, in forming a thin film on a wafer, can reduce impurities or the like adhering to the wafer and a method for manufacturing the...
2017/0162424 APPARATUS OF PROCESSING WORKPIECE IN DEPRESSURIZED SPACE
In a processing apparatus according to one embodiment, a stage is installed inside a process chamber. The stage has a plurality of through-holes formed...
2017/0162423 DESIGN FOR STORING AND ORGANIZING MINIMUM CONTACT AREA FEATURES AND WAFER TRANSFER PINS DURING SYSTEM MAINTENANCE
A tray for storing minimum contact area (MCA) components of a substrate processing system includes a first compartment including at least one of a first lift...
2017/0162422 AMALGAMATED COVER RING
The present disclosure generally relates to generally relates to equipment for performing semiconductor device fabrication, and more particularly, to a cover...
2017/0162421 Transfer Device and Correction Method
A transfer device includes a rotation driving mechanism for rotationally driving a first linear arm and a second linear arm to move a holding part between a...
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