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Patent # Description
2017/0162268 Reduction or Elimination of a Latency Penalty Associated With Adjusting Read Thresholds for Non-Volatile Memory
Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference...
2017/0162267 Data Storage Device and Data Maintenance Method
A data storage device including a flash memory and a controller. The flash memory includes a plurality of pages and a plurality of word lines, wherein each of...
2017/0162266 NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE
A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a row decoder circuit connected to the memory cell array...
2017/0162265 PROGRAMMING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM HISTORY
A method includes determining, internal to a memory device, a number of program pulses required to program a sample of memory cells of the memory device during...
2017/0162264 Method for Managing a Fail Row of the Memory Plane of a Non Volatile Memory and Corresponding Memory Device
A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane,...
2017/0162263 APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
2017/0162262 RESISTIVE MEMORY DEVICE AND OPERATION METHOD THEREOF
A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell...
2017/0162261 PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DATA IN ONE OR MORE LAYERS OF MEMORY
Methods to maintain values representing data in a memory are disclosed. A method may include identifying a plurality of in-use portions of the memory currently...
2017/0162260 METHOD FOR READING OUT A RESISTIVE MEMORY CELL AND A MEMORY CELL FOR CARRYING OUT THE METHOD
A method for reading out a resistive memory cell comprising two electrodes that are spaced from each other by an ion-conducting resistive material was...
2017/0162259 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes a memory device including a plurality of memory blocks, each memory block including a plurality of word lines, each word line being...
2017/0162258 Management of Data Storage in Memory Cells Using a Non-Integer Number of Bits Per Cell
A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally...
2017/0162257 MEMORY DEVICE
According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second...
2017/0162256 SEMICONDUCTOR MEMORY WITH DATA LINE CAPACITIVE COUPLING
A semiconductor memory includes a first data line, a second data line, a first coupling line, a second coupling line, a first plurality of transistors, and a...
2017/0162255 LOW RESISTANCE POWER HEADER WITH REDUCED INSTANTANEOUS VOLTAGE DROP
A power header includes a first line, and a first power-enable control device that comprises a source region and a drain region. The drain region of the first...
2017/0162254 PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY
The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a...
2017/0162253 SYSTEMS, METHODS, AND APPARATUSES FOR PERFORMING REFRESH OPERATIONS
An apparatus is disclosed. The apparatus includes an address counter configured to provide a refresh address to a refresh circuit, wherein the address counter...
2017/0162252 REDUCED TRANSPORT ENERGY IN A MEMORY SYSTEM
A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link...
2017/0162251 ASYMMETRICAL EMPHASIS IN A MEMORY DATA BUS DRIVER
An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The...
2017/0162250 Multilevel Ferroelectric Memory Cell for an Integrated Circuit
An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one...
2017/0162249 METHOD FOR FABRICATING FERROELECTRIC RANDOM-ACCESS MEMORY ON PRE-PATTERNED BOTTOM ELECTRODE AND OXIDATION BARRIER
Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier...
2017/0162248 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a cell array including a plurality of memory cells; a sense amplifier reading data of the memory cell; write drivers...
2017/0162247 DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY
A circuit includes a first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store a first and a...
2017/0162246 METHOD AND APPARATUS FOR PERFORMING SELF-REFERENCED READ IN A MAGNETORESISTIVE RANDOM ACCESS MEMORY
A method of reading information stored in a magnetic memory. In a magnetic memory comprising a magnetic tunnel junction including a first reference layer and a...
2017/0162245 SEMICONDUCTOR SYSTEM
A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a...
2017/0162243 APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
2017/0162242 Method and Apparatus for Adjustment of Current Through a Magnetoresistive Tunnel Junction (MTJ) Based on...
A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially...
2017/0162241 APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME
Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first...
2017/0162240 SYSTEMS, CIRCUITS, AND METHODS FOR CHARGE SHARING
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage...
2017/0162239 SEMICONDUCTOR DEVICE
A semiconductor device includes a voltage hold circuit that raises a second boosted voltage with rise of an output voltage of a booster circuit that generates...
2017/0162238 MEMORY DEVICE FOR PERFORMING CALIBRATION OPERATION
Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured...
2017/0162237 SEMICONDUCTOR APPARATUS HAVING MULTIPLE RANKS WITH NOISE ELIMINATION
A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. One...
2017/0162236 BUFFER MEMORY DEVICE AND DISPLAY DRIVE DEVICE
A buffer memory and display drive device are described herein. In one example, a buffer memory is arranged so that write and read address counters are...
2017/0162235 SYSTEM AND METHOD FOR MEMORY MANAGEMENT USING DYNAMIC PARTIAL CHANNEL INTERLEAVING
Systems and methods are disclosed for providing memory channel interleaving with selective power/performance optimization. One such method comprises...
2017/0162234 DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor...
2017/0162233 Method And Apparatus For Memory Power And/Or Area Reduction
A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A...
2017/0162232 MEMORY DEVICE WITH STRAP CELLS
A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a...
2017/0162231 MEMORY DEVICE
A memory device may be provided. The memory device may include a plurality of channel areas including a plurality of cell array areas. The memory device may...
2017/0162230 INTERACTIVE DIGITAL CAMERA FOR LIVE CROP EDITING AND RECORDING OF VIDEO STREAMS
A camera device comprising a body housing an image-capturing component and a first and second encoder component and a second encoder component coupled to the...
2017/0162229 PLAY METHOD AND DEVICE
An embodiment of the present disclosure discloses a play method and device, wherein the method specifically comprises the steps of a player receiving a calling...
2017/0162228 SYSTEMS AND METHODS FOR MEDIA TRACK MANAGEMENT IN A MEDIA EDITING TOOL
In a media editing device for reorganizing media content and editing the reorganized media content, a plurality of tracks is obtained, where each track...
2017/0162227 METHODS AND APPARATUS FOR REMOTE MOTION GRAPHICS AUTHORING
Methods and apparatus are presented concerning network-accessible services that provide post-production digital compositing and motion graphics authoring to...
2017/0162226 DISPLAY DEVICE AND DRIVE METHOD FOR SAME
An initial current ratio calculation unit obtains an initial current ratio for each pixel based on a current measurement result by a data line drive/current...
2017/0162225 MOTION DETECTION FOR A/V RECORDING AND COMMUNICATION DEVICES
Audio/video (A/V) recording and communication devices according to the present embodiments comprise a processor, a motion sensor, and a camera. In various...
2017/0162224 Multi-Track Data Processor With Iterative Inter-Track Interference Cancellation
An apparatus for two-dimensional magnetic recording includes an array reader comprising a number of read sensors configured to read data from at least one...
2017/0162223 INFORMATION PROCESSING DEVICE, INFORMATION RECORDING MEDIUM, INFORMATION PROCESSING METHOD, AND PROGRAM
To determine whether or not a correct continuous reproduction disk has been attached, and perform control in accordance with a determination result in a data...
2017/0162222 LASER MODE HOPPING DETECTION FOR HEAT-ASSISTED MAGNETIC RECORDING DEVICE
Methods and apparatuses for detecting mode hopping in a laser diode or other optical energy source in heat-assisted magnetic recording. An output power of the...
2017/0162221 Optical Information Recording/Reproduction Device and Optical Information Recording/Reproduction Method
Provided is a recording method with which wasteful consumption of the M number (M/#) of the recording material is prevented, and with which the recording...
2017/0162220 MAGNETIC RECORDING MEDIUM
The magnetic recording medium includes a support and a magnetic layer containing a magnetic powder. The magnetic powder includes at least either of a magnetic...
2017/0162219 ENCODING INFORMATION ON TAPE USING WRITE OFFSET GAPS
As disclosed herein a method for encoding information on tape using write offset gaps. The method includes receiving a request to write a dataset on a tape...
2017/0162218 TWO-MOTOR CO-LOCATED GIMBAL-BASED DUAL STAGE ACTUATION DISK DRIVE SUSPENSIONS WITH MOTOR STIFFENERS
Various embodiments concern a dual stage actuation flexure. The dual stage actuation flexure comprises a flexure having a gimbal. The gimbal comprising a pair...
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