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Patent # Description
2017/0179275 FIN-TYPE SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
The present disclosure relates to a fin-type semiconductor structure which can effectively control a leakage current between a source region and a drain region...
2017/0179274 CHANNEL REPLACEMENT AND BIMODAL DOPING SCHEME FOR BULK FINFET THRESHOLD VOLTAGE MODULATION WITH REDUCED...
A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material...
2017/0179273 SWITCHING DEVICE WITH CHARGE DISTRIBUTION STRUCTURE
A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer...
2017/0179272 Method of Fabricating an Enhancement Mode Group III-Nitride HEMT Device and a Group III-Nitride Structure...
The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One...
2017/0179271 HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)
A high electron mobility transistor (HEMT) device with a highly resistive layer co-doped with carbon (C) and a donor-type impurity and a method for making the...
2017/0179270 FIELD EFFECT TRANSISTOR
A field effect transistor includes a semiconductor stack including a channel provided on a border between a first nitride semiconductor and a second nitride...
2017/0179269 METHOD FOR MAKING III-V NANOWIRE QUANTUM WELL TRANSISTOR
The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a...
2017/0179268 Method of Manufacturing a Bipolar Semiconductor Switch
A method for forming a bipolar semiconductor switch includes providing a semiconductor body which has a main surface, a back surface arranged opposite to the...
2017/0179267 SEMICONDUCTOR DEVICE INCLUDING EMITTER REGIONS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is...
2017/0179266 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region...
2017/0179265 POWER SEMICONDUCTOR DEVICE
An object is to provide a technique that enables suppression of oscillation of a gate signal waveform. A power semiconductor device includes a power...
2017/0179264 Bipolar Transistor
A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body...
2017/0179263 TWO-DIMENSIONAL MATERIAL SEMICONDUCTOR DEVICE
A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a...
2017/0179262 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a...
2017/0179261 METHODS OF FORMING A DEVICE INCLUDING AN INTERFACIAL DIPOLE LAYER
A method of forming an electronic device includes forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect...
2017/0179260 LDMOS DEVICE WITH GRADED BODY DOPING
A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is...
2017/0179259 VERTICAL TRANSISTOR FABRICATION AND DEVICES
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first...
2017/0179258 CHANNEL-LAST REPLACEMENT METAL-GATE VERTICAL FIELD EFFECT TRANSISTOR
A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench...
2017/0179257 JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted ...
2017/0179256 IMPROVING GAP FILL OF METAL STACK IN REPLACEMENT GATE PROCESS
A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate...
2017/0179255 GAP FILL OF METAL STACK IN REPLACEMENT GATE PROCESS
A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate...
2017/0179254 CHANNEL REPLACEMENT AND BIMODAL DOPING SCHEME FOR BULK FINFET THRESHOLD VOLTAGE MODULATION WITH REDUCED...
A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material...
2017/0179253 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device may include: preparing a semiconductor substrate including a doping region; performing tilt implantation using...
2017/0179252 MULTI-THRESHOLD VOLTAGE STRUCTURES WITH A LANTHANUM NITRIDE FILM AND METHODS OF FORMATION THEREOF
Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some...
2017/0179251 NANOWIRE SEMICONDUCTOR DEVICE
A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard...
2017/0179249 SEMICONDUCTOR DEVICE
A semiconductor device is provided that is excellent in semiconductor properties and Schottky characteristics. A semiconductor device includes: a semiconductor...
2017/0179248 HORIZONTAL GATE ALL AROUND NANOWIRE TRANSISTOR BOTTOM ISOLATION
A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an...
2017/0179247 METHOD FOR PRODUCING A HIGH-VOLTAGE TRANSISTOR WITH REDUCED FOOTPRINT, AND CORRESPONDING INTEGRATED CIRCUIT
An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded...
2017/0179246 METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent...
2017/0179245 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a...
2017/0179244 STRUCTURE FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE
A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a...
2017/0179243 STRUCTURE FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE
A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a...
2017/0179242 SEMICONDUCTOR STRUCTURE HAVING A GAS-FILLED GAP
A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a...
2017/0179241 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a...
2017/0179240 METHOD FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE
A structure and method for fabricating a semiconductor device is described. A device structure including a gate structure, a source region and a drain region...
2017/0179239 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor...
2017/0179237 III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER
An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first...
2017/0179236 METHOD OF PRODUCING SILICON CARBIDE EPITAXIAL SUBSTRATE, SILICON CARBIDE EPITAXIAL SUBSTRATE, AND SILICON...
A method of producing a silicon carbide epitaxial substrate includes steps of: preparing a silicon carbide substrate; and forming a silicon carbide layer on...
2017/0179235 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes an n.sup.+ type silicon carbide substrate, and in the substrate an active region where primary current flows and an edge...
2017/0179234 MULTILAYER GRAPHENE, METHOD OF FORMING THE SAME, DEVICE INCLUDING THE MULTILAYER GRAPHENE, AND METHOD OF...
A multilayer graphene, a method of forming the same, a device including the multilayer graphene, and a method of manufacturing the device are provided. In the...
2017/0179233 High Mobility Transport Layer Structures for Rhombohedral Si/Ge/SiGe Devices
An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A...
2017/0179232 III-V TRANSISTOR DEVICE WITH DOPED BOTTOM BARRIER
A method for forming a semiconductor device comprising forming a sacrificial gate stack on a channel region of first layer of a substrate, forming a spacer...
2017/0179231 PROTECTING TRANSISTOR ELEMENTS AGAINST DEGRADING SPECIES
A technique comprising: providing a stack of layers defining at least (a) source and drain electrodes, (b) gate electrode, and (c) semiconductor channel of at...
2017/0179230 JUNCTION INTERLAYER DIELECTRIC FOR REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICES
A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the...
2017/0179229 SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR
A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of...
2017/0179228 STRAIN COMPENSATION IN TRANSISTORS
Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The...
2017/0179227 DIELECTRICALLY ISOLATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to a dielectrically isolated semiconductor device and a method for manufacturing the same. The dielectrically isolated...
2017/0179226 ULTRASOUND T/R ISOLTATION DISOLATOR WITH FAST RECOVERY TIME ON SOI
A semiconductor disolator device is provided. The device may include a silicon-on-insulator (SOI) substrate, a body layer disposed on the SOI substrate, a...
2017/0179225 SEMICONDUCTOR DEVICE HAVING A SUPER JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are...
2017/0179223 SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
[Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area...
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