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Patent # Description
2017/0179171 SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of...
2017/0179170 PIXEL FOR CMOS IMAGE SENSOR AND IMAGE SENSOR INCLUDING THE SAME
A pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a semiconductor substrate having a first surface and a third surface formed...
2017/0179169 DIRECT INTEGRATION OF PHOTOVOLTAIC DEVICE INTO CIRCUIT BOARD
Aspects relate to a system and a method of manufacturing an integrated device. The method includes providing a circuit board, configuring an upper surface of...
2017/0179168 DISPLAY DEVICE
According to one embodiment, a display device includes an insulating substrate, display function layer disposed above the insulating substrate, reflective...
2017/0179167 SEMICONDUCTOR DEVICE
Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a...
2017/0179166 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS
The present invention relates to an array substrate, which comprises: a display region and a drive circuit region; the drive circuit region comprises GOA...
2017/0179165 PIXEL STRUCTURE AND DISPLAY DEVICE
The present application discloses a pixel structure and a display device. The pixel structure includes: a scan line having a branch structure; and a...
2017/0179164 METHOD OF MANUFACTURING THIN-FILM TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND FLAT PANEL DISPLAY APPARATUS
A method of manufacturing a thin-film transistor includes forming an oxide semiconductor on a substrate, stacking an insulating layer and a metal layer on the...
2017/0179163 LOCAL SOI FINS WITH MULTIPLE HEIGHTS
A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process...
2017/0179162 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
A semiconductor device (100) according to the present invention is a semiconductor device with a thin-film transistor (10), and includes: a gate electrode (62)...
2017/0179161 DISPLAY DEVICE
To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction...
2017/0179160 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SAME
A semiconductor device with reduced power consumption and a display device including the semiconductor are provided. The semiconductor device generates a bias...
2017/0179159 DISPLAY DEVICE
According to one embodiment, a display device includes a first substrate including a support substrate, a light shield, an insulating substrate disposed above...
2017/0179158 TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
A transistor array panel includes a transistor disposed on a substrate. The transistor includes a gate electrode, a source electrode, a drain electrode, a...
2017/0179157 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support...
2017/0179156 STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a...
2017/0179155 3D MEMORY DEVICE AND STRUCTURE
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second...
2017/0179154 THROUGH-MEMORY-LEVEL VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
2017/0179153 THROUGH-MEMORY-LEVEL VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
2017/0179152 THROUGH-MEMORY-LEVEL VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
2017/0179151 THROUGH-MEMORY-LEVEL VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
2017/0179150 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; and a plate portion. The stacked body includes a...
2017/0179149 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure...
2017/0179148 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure,...
2017/0179147 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third...
2017/0179146 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF
A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of...
2017/0179145 SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURE THEREOF
The invention provides a method for use in forming a semiconductor device, the semiconductor device comprising a primary area and a periphery area, the method...
2017/0179144 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes channel layers arranged in a first direction and a second direction intersecting the first direction; stacked insulating layers...
2017/0179143 MEMORY HAVING A CONTINUOUS CHANNEL
The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical...
2017/0179142 SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD
A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein...
2017/0179141 Method Of Making Split Gate Non-volatile Memory Cell With 3D FINFET Structure
A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side...
2017/0179140 SEMICONDUCTOR DEVICE
A nonvolatile logic cell (nonvolatile storage element) 21 includes ferroelectric capacitors 25 and MOSFETs 26. A plurality of ferroelectric dummy capacitors 32...
2017/0179139 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a...
2017/0179138 COMPACT CMOS ANTI-FUSE MEMORY CELL
A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N- well and an anti-fuse cell formed on the N- well. The anti-fuse cell includes...
2017/0179137 SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION
An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon...
2017/0179135 STATIC RANDOM ACCESS MEMORY DEVICE WITH VERTICAL FET DEVICES
An SRAM includes an SRAM array comprising a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect...
2017/0179134 LAYOUT OF STATIC RANDOM ACCESS MEMORY CELL
A static random access memory (SRAM) cell is defined by first and second boundaries disposed opposite to each other and third and fourth boundaries disposed...
2017/0179133 NON-UNIFORM GATE OXIDE THICKNESS FOR DRAM DEVICE
Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed...
2017/0179132 SEMICONDUCTOR DEVICE
Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including...
2017/0179131 SEMICONDUCTOR INTEGRATED CIRCUIT
The present disclosure relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes a substrate, a first transistor and a first...
2017/0179130 ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES
A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The...
2017/0179129 METHOD AND DEVICE FOR REDUCING FINFET SELF-HEATING EFFECT
A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming a diamond film on the substrate, etching the diamond...
2017/0179128 NANOSHEET CMOS WITH HYBRID ORIENTATION
A semiconductor structure is provided that includes a substrate comprising a first semiconductor material having a first crystallographic orientation and a...
2017/0179127 SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF FABRICATING SAME
An aspect of the disclosure includes a semiconductor structure comprising: a set of fins on a substrate, the set of fins including a relaxed silicon germanium...
2017/0179126 INTEGRATED CIRCUIT HAVING CHEMICALLY MODIFIED SPACER SURFACE
A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack...
2017/0179125 METHOD TO FORM DUAL TIN LAYERS AS PFET WORK METAL STACK
A method of making a semiconductor device includes growing an interfacial layer on a substrate; depositing a first titanium nitride (TiN) layer on the...
2017/0179124 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first...
2017/0179123 Fin Field Effect Transistor (FinFET) Device Structure with Uneven Gate Structure
A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the...
2017/0179122 SEMICONDUCTOR DEVICE WITH LOCAL INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor device having a local interconnect structure includes providing a semiconductor substrate having a gate on an active...
2017/0179120 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are...
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