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Patent # Description
2017/0179119 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a conductor, and a contact etch stop layer....
2017/0179118 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin...
2017/0179117 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a core device, and an input/output (I/O) device. The core device is disposed on the substrate. The core device...
2017/0179116 INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a...
2017/0179115 SEMI-FLOATING-GATE POWER DEVICE AND MANUFACTURING METHOD THEREFOR
The disclosure belongs to the technical field of semiconductor power devices, specifically relates to a semi-floating-gate power device, and comprises the...
2017/0179114 FABRICATION METHOD OF A STACK OF ELECTRONIC DEVICES
This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first...
2017/0179113 METHOD FOR FABRICATING A JFET TRANSISTOR WITHIN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT
An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is...
2017/0179112 SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes...
2017/0179111 SEMICONDUCTOR DEVICE AND AN INTEGRATED CIRCUIT COMPRISING AN ESD PROTECTION DEVICE, ESD PROTECTION DEVICES AND...
A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in...
2017/0179109 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In a circuit portion, a p.sup.+-type diffusion region penetrates, in the depth direction, an n.sup.--type base region on the front side of a base substrate and...
2017/0179108 SEMICONDUCTOR DEVICE
A semiconductor device according to the present invention includes: a substrate; a plurality of trenches formed in the substrate; and a plurality of functional...
2017/0179107 TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED BREAKDOWN VOLTAGE
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first...
2017/0179106 ELECTROSTATIC PROTECTION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC DEVICE
Provided is an electrostatic protection circuit that has little leakage current under normal operation and allows a trigger voltage to be set comparatively...
2017/0179105 SEMICONDUCTOR DEVICE AND LAYOUT THEREOF
A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first...
2017/0179104 ROUTING FOR THREE-DIMENSIONAL INTEGRATED STRUCTURES
A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second...
2017/0179103 FLEXIBLE ELECTRONIC SYSTEM WITH WIRE BONDS
Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an...
2017/0179102 SYSTEM IN PACKAGE
An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using...
2017/0179101 BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE
A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die,...
2017/0179100 OPTICAL SYSTEMS FABRICATED BY PRINTING-BASED ASSEMBLY
Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific...
2017/0179098 METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE
A method of fabricating a semiconductor package includes mounting a plurality of semiconductor chips on a substrate in a stripped state, forming a mold layer...
2017/0179097 Making Semiconductor Devices with Alignment Bonding and Substrate Removal
Embodiments include a manufacturing method of making a semiconductor device via multiple stages of alignment bonding and substrate removal. One example is an...
2017/0179096 MANUFACTURE OF WAFER - PANEL DIE PACKAGE ASSEMBLY TECHNOLOGY
Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to ...
2017/0179095 SEMICONDUCTOR APPARATUS
A semiconductor apparatus reduces the effect of inductances and induced magnetic fields, and causes a large current to flow from one device to another device....
2017/0179094 MAGNETIC SMALL FOOTPRINT INDUCTOR ARRAY MODULE FOR ON-PACKAGE VOLTAGE REGULATOR
An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements...
2017/0179093 Inter-Chip Alignment
First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface...
2017/0179092 Hybrid Display using Inorganic Micro Light Emitting Diodes (uLEDs) and Organic LEDs (OLEDs)
A hybrid light emitting diode (LED) display and fabrication method are provided. The method forms a stack of thin-film layers overlying a top surface of a...
2017/0179091 OPTOELECTROIC SEMICONDUCTOR CHIP AND METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP
An optoelectronic semiconductor chip includes a semiconductor layer sequence with an upper face and a lower face opposite the upper face, wherein the...
2017/0179090 SOLID STATE DEVICE MINIATURIZATION
One or more example embodiments of miniaturized electric devices are disclosed. in some example embodiments, the electric device includes a first thin...
2017/0179089 MULTI-LAYER POWER CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT
An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive...
2017/0179088 WIRE BOND FREE WAFER LEVEL LED
A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two...
2017/0179087 ARRAY-TYPE DOUBLE-SIDE LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF AND DOUBLE-SIDE DISPLAY DEVICE
The present invention relates to an array-type double-side light-emitting device, a manufacturing method thereof and a double-side display device. The...
2017/0179086 LIGHT-EMITTING DEVICE
A light-emitting device configured to electrically connect to an external circuit and having: a first light-emitting structure; a second light-emitting...
2017/0179085 OPTICAL SYSTEMS FABRICATED BY PRINTING-BASED ASSEMBLY
Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific...
2017/0179083 Semiconductor Packaging Structure and Method
A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A...
2017/0179082 METHOD FOR INTERCONNECTING STACKED SEMICONDUCTOR DEVICES
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The...
2017/0179081 FLIPPED DIE STACKS WITH MULTIPLE ROWS OF LEADFRAME INTERCONNECTS
Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and...
2017/0179080 SEMICONDUCTOR PACKAGE INTERPOSER HAVING ENCAPSULATED INTERCONNECTS
Semiconductor package interposers having high-density and high-aspect ratio encapsulated interconnects, and semiconductor package assemblies incorporating such...
2017/0179079 HIGH-SPEED SEMICONDUCTOR MODULES
A semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module...
2017/0179078 SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME
A semiconductor package and or method of fabricating the semiconductor package may be provided. The semiconductor package may include a first die, at least one...
2017/0179077 ADVANCED CHIP TO WAFER STACKING
A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first...
2017/0179076 REDUCTION OF DEFECTS IN WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) DEVICES
Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces...
2017/0179075 COPPER WIRE AND ELECTRODE JOINING METHOD AND JOINT STRUCTURE
With this copper wire joining method, a rubbed portion on which a coating remains between an electrode and a core wire is formed on the electrode. Then, after...
2017/0179074 ELECTRONIC DEVICES AND PROCESS OF FORMING THE SAME
A process of forming an electronic device includes providing a wire comprising a first ball at an end thereof, operating on the first ball to modify a surface...
2017/0179073 METHOD FOR PERFORMING DIRECT BONDING BETWEEN TWO STRUCTURES
This method includes steps a) providing the first structure and second structure, the first structure including a surface on which a silicon layer is formed;...
2017/0179072 SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS
A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first...
2017/0179070 THERMOCOMPRESSION BONDING USING PLASMA GAS
Described herein are devices and techniques for thermocompression bonding. A device can include a housing, a platform, and a plasma jet. The housing can define...
2017/0179069 BALL GRID ARRAY SOLDER ATTACHMENT
Reflow Grid Array (RGA) technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a ball grid array (BGA)...
2017/0179068 STRUCTURES TO ENABLE A FULL INTERMETALLIC INTERCONNECT
A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder...
2017/0179067 SEMICONDUCTOR PACKAGE ALIGNMENT FRAME FOR LOCAL REFLOW
Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The...
2017/0179066 BULK SOLDER REMOVAL ON PROCESSOR PACKAGING
Reflow Grid Array technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a BGA package. The interposer...
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