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Patent # Description
2017/0179065 ELECTRICAL INTERCONNECTIONS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
An electrical interconnection includes a wire loop having a first end bonded to a first bonding site using a first bonding portion, and a second end bonded to...
2017/0179064 BONDING WIRE FOR SEMICONDUCTOR DEVICE
A bonding wire for a semiconductor device including a coating layer having Pd as a main component on the surface of a Cu alloy core material and a skin alloy...
2017/0179063 COUPLING ELEMENT, INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATION THEREFOR
A coupling element for providing external coupling to a semiconductor die within an integrated circuit package. The coupling element comprises a flexible...
2017/0179062 SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction...
2017/0179061 NANOWIRES FOR PILLAR INTERCONNECTS
An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may...
2017/0179060 SEMICONDUCTOR DEVICE
A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and...
2017/0179058 BUMP STRUCTURE HAVING FIRST PORTION OF COPPER AND SECOND PORTION OF PURE TIN COVERING THE FIRST PORTION, AND...
A bump structure includes a pad. A passivation layer covers a perimeter of the pad. The passivation layer includes an opening exposing an area of the pad. A...
2017/0179057 FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF
Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a...
2017/0179056 SEMICONDUCTOR DEVICE WITH A BUMP CONTACT ON A TSV COMPRISING A CAVITY AND METHOD OF PRODUCING SUCH A...
The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3)...
2017/0179055 SEMICONDUCTOR STRUCTURE
The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A...
2017/0179054 Semiconductor Device Structure Comprising a Plurality of Metal Oxide Fibers and Method for Forming the Same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive...
2017/0179053 SELF-ALIGNED UNDER BUMP METAL
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer,...
2017/0179052 Method of Forming Metal Pads with Openings in Integrated Circuits Including Forming a Polymer Extending into a...
A device includes a metal pad, and a passivation layer comprising portions overlapping edge portions of the metal pad. The metal pad and the passivation layer...
2017/0179051 Contact Pad for Semiconductor Devices
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad...
2017/0179050 SEMICONDUCTOR DEVICE
A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a...
2017/0179049 POWER GRID BALANCING APPARATUS, SYSTEM AND METHOD
A semiconductor apparatus for power distribution on a die, the semiconductor apparatus, comprising a first die, wherein the first die comprises a first...
2017/0179048 STACKED INDUCTOR-ELECTRONIC PACKAGE ASSEMBLY AND TECHNIQUE FOR MANUFACTURING SAME
An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the...
2017/0179046 HIGH YIELD SUBSTRATE ASSEMBLY
In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the...
2017/0179045 METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in...
2017/0179044 INTEGRATED CIRCUIT
An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the...
2017/0179043 SYSTEMS, METHODS AND DEVICES FOR STIFFENER CONSTRUCTION FOR USE IN PICK AND PLACE MEDIA
Creating surface variations on a stiffener in a stack reduces inter-stiffener sticking and stiffener stack tilt in pick and place media. The surface variations...
2017/0179042 PROTECTION OF ELEMENTS ON A LAMINATE SURFACE
A module includes a core, a buildup layer having a top and a bottom, the bottom contacting the core, a solder mask layer contacting the top, the solder mask...
2017/0179041 SEMICONDUCTOR PACKAGE WITH TRENCHED MOLDING-BASED ELECTROMAGNETIC INTERFERENCE SHIELDING
Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may...
2017/0179040 PERFORATED CONDUCTIVE MATERIAL FOR EMI SHIELDING OF SEMICONDUCTOR DEVICE AND COMPONENTS
An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a...
2017/0179039 VERTICAL INTERCONNECTS FOR SELF SHIELDED SYSTEM IN PACKAGE (SIP) MODULES
A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield...
2017/0179038 SEMICONDUCTOR DEVICE PACKAGE SUBSTRATE HAVING A FIDUCIAL MARK
A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes...
2017/0179037 SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at...
2017/0179036 Conformal Amorphous Silicon As Nucleation Layer For W ALD Process
Methods for depositing a metal film comprising forming an amorphous silicon layer as a nucleation layer and/or glue layer on a substrate. Some embodiments...
2017/0179035 METHOD OF PLANARIZING RECESSES FILLED WITH COPPER
A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper...
2017/0179034 COMPOSITE MANGANESE NITRIDE / LOW-K DIELECTRIC CAP
A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the...
2017/0179032 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one...
2017/0179031 Electronic Component Of Integrated Circuitry And A Method Of Forming A Conductive Via To A Region Of...
An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface....
2017/0179030 Methods of Forming Metal Pad Structures Over TSVS to Reduce Shorting of Upper Metal Layers
Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad...
2017/0179029 INCREASED CONTACT ALIGNMENT TOLERANCE FOR DIRECT BONDING
A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and...
2017/0179028 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second...
2017/0179027 MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND MEMORY PACKAGE INCLUDING THE SAME
A memory device includes a substrate, and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first...
2017/0179026 THROUGH-MEMORY-LEVEL VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
2017/0179025 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a...
2017/0179024 DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICAL SEMICONDUCTOR DEVICES
Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a...
2017/0179023 HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form...
2017/0179022 WIRING BOARD AND SEMICONDUCTOR DEVICE
A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first...
2017/0179020 Method of Forming Trenches
A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a...
2017/0179019 INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP
Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at...
2017/0179018 SEMICONDUCTOR MODULE
A semiconductor module includes a plurality of semiconductor chips that include gate electrodes on front surfaces, a gate terminal that receives a control...
2017/0179017 SEMICONDUCTOR PACKAGE
A semiconductor package includes a circuit board, a semiconductor chip, a heat spreading layer, an encapsulant layer, a plurality of conductive connections,...
2017/0179016 Carrier for an Electrical Component
A carrier for an electrical component, including a substrate having a surface, with an electrically conductive contact zone arranged on the surface of the...
2017/0179015 ELEMENT PLACE ON LAMINATES
A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not...
2017/0179014 SUBSTRATE FOR STACKED MODULE, STACKED MODULE, AND METHOD FOR MANUFACTURING STACKED MODULE
A substrate for a stacked module includes a stacked insulator in which a plurality of insulator layers mainly composed of a thermoplastic resin are stacked, a...
2017/0179013 WIRING BOARD, AND SEMICONDUCTOR DEVICE
A wiring board includes: a core substrate including: a metal plate having first through holes; a first insulating layer covering an upper surface and a lower...
2017/0179012 TERMINAL STRUCTURE AND WIRING SUBSTRATE
A terminal structure of a wiring substrate includes a wiring layer, a protective insulation layer including an opening that partially exposes an upper surface...
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