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Patent # Description
2017/0200759 CMOS Image Sensors
A complementary metal oxide semiconductor (CMOS) image sensor is provided that includes a substrate including a first surface, a second surface facing the...
2017/0200758 CMOS IMAGE SENSOR AND FABRICATION METHOD THEREOF
The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing...
2017/0200757 IMAGE SENSORS
An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have...
2017/0200756 SEMICONDUCTOR DEVICE STRUCTURE WITH STACKED SEMICONDUCTOR DIES
A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die and a second semiconductor die. The...
2017/0200755 Flip-Chip Image Sensor Package
A flip-chip image-sensor package includes a substrate, a coverglass, a conductive layer, and an image sensor. The substrate has an aperture therethrough and a...
2017/0200754 SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first...
2017/0200753 Image Sensor and Computing System Having the Same
An image sensor includes a light receiving element, an anti-reflection layer, a high refractive pattern, a color filter, and a micro lens. The light receiving...
2017/0200752 MONOLITHIC INTEGRATION TECHNIQUES FOR FABRICATING PHOTODETECTORS WITH TRANSISTORS ON SAME SUBSTRATE
Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a...
2017/0200751 Energy Harvesting Devices and Method of Fabrication Thereof
An apparatus and method pertaining to a perpetual energy harvester. The harvester absorbs ambient infrared radiation and provides continual power regardless of...
2017/0200750 METHOD FOR MANUFACTURING ARRAY SUBSTRATE
Provided is a method for manufacturing an array substrate, in which a planarization layer mask includes a strip pattern that is provided for forming a groove...
2017/0200749 METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE
A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate...
2017/0200748 LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE
To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an...
2017/0200747 DISPLAY DEVICE INCLUDING THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
A TFT array panel of a display device includes a first substrate, a first electrode disposed on the first substrate, a first insulating layer including a first...
2017/0200746 Thin Film Transistor, Manufacturing Method Thereof, Display Substrate and Display Device
A thin film transistor (TFT), a manufacturing method thereof, a display substrate and a display device are disclosed. The TFT includes: a gate electrode; a...
2017/0200745 THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE
A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The method comprises forming an active layer...
2017/0200744 METHODS FOR FORMING FINS FOR METAL OXIDE SEMICONDUCTOR DEVICE STRUCTURES
Embodiments of the present disclosure relate to non-planar semiconductor device structures having fins. In one embodiment, a semiconductor device includes a...
2017/0200743 SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AND A SECOND TRANSISTOR
A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of...
2017/0200742 ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF
An organic light emitting diode display having a lightly doped region formed in a transistor for simplifying manufacturing process and reducing manufacturing...
2017/0200741 PIXEL STRUCTURE
An active device of a pixel structure includes a semiconductor layer, an insulation layer covering the semiconductor layer, a gate electrode disposed on the...
2017/0200740 FIELD RELAXATION THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS INCLUDING THE...
A thin film transistor includes a semiconductor pattern formed on a substrate, the semiconductor pattern being formed of an oxide semiconductor and including a...
2017/0200739 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate has a display...
2017/0200738 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around...
2017/0200737 Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within...
2017/0200736 SEMICONDUCTOR MEMORY DEVICES
A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend...
2017/0200735 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
The memory string comprises: a plurality of control gate electrodes stacked on the substrate and extending in a first direction and a second direction parallel...
2017/0200734 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING THE SAME
One embodiment includes a plurality of memory cells and a plurality of conducting layers. The memory cells are three-dimensionally disposed on a semiconductor...
2017/0200733 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first...
2017/0200732 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
According to an embodiment, a method of manufacturing a semiconductor device includes forming a layered body by alternately stacking a first film and a second...
2017/0200731 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
According to an embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film, a first structure body, and a first...
2017/0200730 ELECTRONIC CHIP MANUFACTURING METHOD
Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the...
2017/0200729 INTEGRATED CIRCUIT AND PROCESS THEREOF
An integrated circuit process includes the following steps. A substrate including a flash cell area and a logic area is provided. A first sacrificial gate on...
2017/0200728 METHOD OF MANUFACTURING AN EEPROM DEVICE
A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a first dielectric layer having a first thickness on...
2017/0200727 SEMICONDUCTOR DEVICES
A semiconductor device is disclosed. The semiconductor device including writing and reading gate electrodes respectively on first and second active regions on...
2017/0200726 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the...
2017/0200725 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other,...
2017/0200724 MEMORY DEVICE AND FABRICATING METHOD THEREOF
A memory device and a method for fabricating the same are provided. The memory device includes a substrate and an isolation structure. The substrate has at...
2017/0200723 SEMICONDUCTOR DEVICES HAVING A GATE STRUCTURE AND A CONDUCTIVE LINE AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes an active pattern. A first source or drain region and a second source or drain region are formed at upper portions of the...
2017/0200722 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps...
2017/0200721 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well,...
2017/0200720 LOW RESISTIVE ELECTRODE FOR AN EXTENDABLE HIGH-K METAL GATE STACK
In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate;...
2017/0200719 STRUCTURE AND METHOD TO SUPPRESS WORK FUNCTION EFFECT BY PATTERNING BOUNDARY PROXIMITY IN REPLACEMENT METAL GATE
A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second...
2017/0200718 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure,...
2017/0200717 SEMICONDUCTOR LAYOUT STRUCTURE
A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended...
2017/0200716 3D SEMICONDUCTOR DEVICE AND STRUCTURE
An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer...
2017/0200715 SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE
An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single...
2017/0200714 GATE PLANARITY FOR FINFET USING DUMMY POLISH STOP
A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes...
2017/0200713 FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH INTEGRATED GATE CONNECTED DIODES
A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect...
2017/0200712 LOW DYNAMIC RESISTANCE LOW CAPACITANCE DIODES
A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5...
2017/0200711 SYSTEMS AND METHODS FOR EFFICIENT TRANSFER OF SEMICONDUCTOR ELEMENTS
Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The...
2017/0200710 OPTICAL MODULE
[Object] To suppress appearance of a ghost. [Solving Means] The present optical module includes a sensor configured to pick up an image of an image pickup object,...
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