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Patent # Description
2017/0200709 FLEXIBLE DISPLAY DEVICE
A flexible display device is disclosed. In one aspect, the display device includes a flexible display panel including a display substrate, wherein the display...
2017/0200708 LED LIGHT SOURCE FOR AUTOMOTIVE APPLICATION
Proposed is a light source comprising first and second LED light sources. Each of the first and second LED light sources have: a semiconductor diode structure...
2017/0200707 Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent...
Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are...
2017/0200706 Light Source Module
A light source module according to an embodiment includes: a flexible printed circuit board that has first and second pads; and a plurality of light emitting...
2017/0200705 POWER DEVICE AND PREPARATION METHOD THEREOF
A power device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power device further includes a substrate...
2017/0200704 SEMICONDUCTOR DEVICE
A semiconductor device 10 includes: multi-layered substrates 12 each having a circuit board 12c; control terminals 14 whose one end is fixed on the circuit...
2017/0200703 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
To miniaturize metal columns. A semiconductor device includes a metal column (14) that extends in a stretching direction; a polymer layer (16) that surrounds...
2017/0200702 POWER AND GROUND DESIGN FOR THROUGH-SILICON VIA STRUCTURE
In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first...
2017/0200700 Interconnect Structures for Assembly of Multi-Layer Semiconductor Devices
A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second...
2017/0200699 SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING
A semiconductor structure in the form of a die comprises a silicon-containing core having a first surface, an opposite second surface and a peripheral edge...
2017/0200698 THREE-DIMENSIONAL HYBRID PACKAGING WITH THROUGH-SILICON-VIAS AND TAPE-AUTOMATED-BONDING
A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a...
2017/0200697 SEMICONDUCTOR DEVICE STRUCTURE
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second...
2017/0200696 MULTI-CHIP PACKAGE WITH INTERCONNECTS EXTENDING THROUGH LOGIC CHIP
A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having...
2017/0200695 APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE
A method of processing a substrate that displays out-gassing when placed in a vacuum includes placing the substrate in a vacuum and performing an out-gassing...
2017/0200694 WIRE BONDED ELECTRONIC DEVICES TO ROUND WIRE
A disclosed circuit arrangement includes a flexible substrate. A layer of pressure sensitive adhesive (PSA) is directly adhered to a first major surface of the...
2017/0200693 ELECTRONIC COMPONENT
An electronic component includes a base, a laminate of a plurality of conductive metal material layers, and a solder layer made of Au--Sn alloy solder. The...
2017/0200692 POWER OVERLAY STRUCTURE HAVING WIREBONDS AND METHOD OF MANUFACTURING SAME
A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL...
2017/0200691 POWER MODULE
A power module is fabricated, employing a clad metal that is formed by pressure-laminating aluminum and copper, in such a manner that the aluminum layer of the...
2017/0200690 BONDING WIRE FOR SEMICONDUCTOR DEVICE
There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material...
2017/0200689 BONDING WIRE FOR SEMICONDUCTOR DEVICE
A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element...
2017/0200688 SEMICONDUCTOR PACKAGE HAVING A BUMP BONDING STRUCTURE
A semiconductor package may be provided. The semiconductor package may include a substrate having a first surface over which bond fingers are arranged, the...
2017/0200687 Mechanisms for Forming Post-Passivation Interconnect Structure
Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also...
2017/0200686 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Disclosed are a semiconductor device and a manufacturing method thereof, which can easily increase the number of input/output pads by increasing regions for...
2017/0200685 MICROELECTRONIC PACKAGE DEBUG ACCESS PORTS AND METHODS OF FABRICATING THE SAME
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,...
2017/0200684 MONOLITHIC INTEGRATION OF III-V CELLS FOR POWERING MEMORY ERASURE DEVICES
A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor...
2017/0200683 SEMICONDUCTOR WAFER, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR WAFER
A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first...
2017/0200682 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top...
2017/0200681 MANUFACTURING METHOD OF DISPLAY PANEL AND BONDING CUTTING DEVICE
The present application provides a manufacturing method of a display panel and a bonding cutting device, belongs to a field of display technology, and can...
2017/0200680 WAFER MARKING METHOD
Disclosed is a wafer marking method using a laser for marking a wafer having processing tape attached thereto. The disclosed laser marking method comprises the...
2017/0200679 Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates
The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when...
2017/0200678 FLEXIBLE SUBSTRATE FOR PACKAGING AND PACKAGE
The present invention provides a flexible substrate for packaging and a package. The flexible substrate for packaging includes a bendable region provided in a...
2017/0200677 MICROELECTRONIC STRUCTURES HAVING LAMINATED OR EMBEDDED GLASS ROUTING STRUCTURES FOR HIGH DENSITY PACKAGING
Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass...
2017/0200676 THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may...
2017/0200675 SEMICONDUCTOR DEVICES INCLUDING A THROUGH VIA STRUCTURE AND METHODS OF FORMING THE SAME
Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor...
2017/0200674 METHOLODOGY FOR PROFILE CONTROL AND CAPACITANCE REDUCTION
Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric...
2017/0200673 Capacitor Embedded with Nanocrystals
The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and...
2017/0200672 Interposer having a Pattern of Sites for Mounting Chiplets
The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site...
2017/0200671 CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD
A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of...
2017/0200670 EMBEDDING THIN CHIPS IN POLYMER
Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a...
2017/0200669 PROCESS FOR MANUFACTURING A PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a...
2017/0200668 FLOW CHANNEL MEMBER, AND HEAT EXCHANGER AND SEMICONDUCTOR MODULE EACH USING SAME
[Object] Provided are a flow channel member having high heat-exchange efficiency in addition to high corrosion resistance and high mechanical characteristics,...
2017/0200667 Photopatternable Silicones For Wafer Level Z-Axis Thermal Interposer
Methods for fabrication of thermal interposers, using a low stress photopatternable silicone are provided, for use in production of electronic products that...
2017/0200666 SEMICONDUCTOR CHIP PACKAGE COMPRISING LATERALLY EXTENDING CONNECTORS
A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation...
2017/0200665 INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature...
2017/0200664 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding...
2017/0200663 CARBON COATED HEAT CONDUCTING MATERIAL
A carbon-coated thermal conductive material includes a coating layer comprising amorphous carbon on a surface of a thermal conductive material, wherein the...
2017/0200662 PACKAGE
A package includes: a semiconductor element; a case having an opening and housing the semiconductor element; and a lid having a rectangular parallelepiped...
2017/0200661 WATERS HAVING A DIE REGION AND A SCRIBE-LINE REGION ADJACENT TO THE DIE REGION
A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive...
2017/0200660 METHOD AND SYSTEM FOR THERMAL CONTROL OF DEVICES IN AN ELECTRONICS TESTER
A tester apparatus is provided. Slot assemblies are removably mounted to a frame. Each slot assembly allows for individual heating and temperature control of a...
2017/0200659 POROUS UNDERFILL ENABLING REWORK
The disclosure generally relates to methods for manufacturing a filled gap region or cavity between two surfaces forming a device microchip. In one embodiment,...
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