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Patent # Description
2017/0200658 METHODS OF INSPECTING SUBSTRATES AND SEMICONDUCTOR FABRICATION METHODS INCORPORATING THE SAME
A method of inspecting a substrate includes irradiating light onto a substrate that has experienced a first process, obtaining spectral data of the light...
2017/0200657 INTEGRATED CIRCUITS AND METHODS THEREFOR
Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC)...
2017/0200656 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
The present disclosure provides a method for fabricating a fin field-effect transistor (fin-FET), including: providing a substrate having a plurality of...
2017/0200655 SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD
A semiconductor device may include a substrate, a p-channel device, and an n-channel device. The p-channel device may include a first metal member, a first...
2017/0200654 LOW RESISTIVE ELECTRODE FOR AN EXTENDABLE HIGH-K METAL GATE STACK
In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate;...
2017/0200653 CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM
Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include ...
2017/0200652 SEMICONDUCTOR DEVICE HAVING WORK-FUNCTION METAL AND METHOD OF FORMING THE SAME
In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on...
2017/0200651 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns,...
2017/0200650 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURE AND PRODUCT THEREOF
A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer,...
2017/0200649 TRANSISTOR WITH SOURCE-DRAIN SILICIDE PULLBACK
The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are...
2017/0200648 METHOD OF MANUFACTURING A SUBSTRATE
A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially...
2017/0200647 DICING METHOD FOR WAFER-LEVEL PACKAGING AND SEMICONDUCTOR CHIP WITH DICING STRUCTURE ADAPTED FOR WAFER-LEVEL...
A semiconductor substrate (1) is provided with integrated circuits. Dicing trenches (7) are formed in the substrate (1) between the integrated circuits, a...
2017/0200646 INTEGRATED CIRCUITS AND MOLDING APPROACHES THEREFOR
Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable...
2017/0200645 METHOD OF MANUFACTURING OF A SIDEWALL OPENING OF AN INTERCONNECT OF A SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An...
2017/0200644 THROUGH ELECTRODE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Embodiments provided are a through electrode that can be manufactured by a method not including the step of removing a side-wall insulating film formed at the...
2017/0200643 ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE
A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the...
2017/0200642 CO OR NI AND CU INTEGRATION FOR SMALL AND LARGE FEATURES IN INTEGRATED CIRCUITS
In one embodiment of the present disclosure, a method for depositing metal in a feature on a workpiece is provided. The method includes electrochemically...
2017/0200641 Self-Aligned Double Spacer Patterning Process
Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a...
2017/0200640 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises...
2017/0200639 METHOD OF MANUFACTURING POROUS BODY, POROUS BODY, METHOD OF MANUFACTURING DEVICE, DEVICE, METHOD OF...
Provided are a method of manufacturing a porous body capable of easily manufacturing a porous body, a porous body, a method of manufacturing a device, a...
2017/0200638 METHODS FOR PROVIDING LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS
A method of forming at least one lithography feature, the method including: providing at least one lithography recess on a substrate, the or each lithography...
2017/0200637 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film...
2017/0200636 VIA PATTERNING USING MULTIPLE PHOTO MULTIPLE ETCH
A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a...
2017/0200635 FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks...
2017/0200634 METHOD OF MANUFACTURING SOI WAFER
A method of manufacturing an SOI wafer, including (a) forming a thermal oxide film on an SOI layer of an SOI wafer by a heat treatment under an oxidizing gas...
2017/0200633 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH NANO-GAPS
A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above...
2017/0200632 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a dielectric layer is formed on the substrate, and an opening is...
2017/0200631 SAMPLE-HOLDING DEVICE, METHOD FOR MANUFACTURING SOLAR CELL, AND METHOD FOR MANUFACTURING SOLAR CELL MODULE
A sample-holding device for holding and lifting a sample includes a sample-holding surface facing the sample; and a positioning member provided at a peripheral...
2017/0200630 SAMPLE TRANSFER SYSTEM AND SOLAR CELL PRODUCTION METHOD
A sample transfer system includes a sample-mounting member mounting a sample thereonto; and a sample-moving device lifting the sample to move the sample...
2017/0200629 ADHESIVE SHEET AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT
An adhesive sheet is provided that is capable of inhibiting scraping up of an adhesive in the dicing step, does not cause chip detachment during dicing...
2017/0200628 LAYERED BODY OF TEMPORARY ADHESIVE
A temporary adhesive is good peelability, heat resistance and cleaning removability after polishing of the rear surface of the wafer. A layered body for...
2017/0200627 SYSTEM AND METHOD FOR SELECTIVE ZAPPING
A system for zapping a wafer, the system includes a pulse generator; a sensor; a first conductive interface; a second conductive interface; a controller;...
2017/0200626 Carrier Buffering Device and Buffering Method
Without a lateral transfer mechanism in a local vehicle, the buffering capacity of a temporary storage apparatus is increased. The temporary storage apparatus...
2017/0200625 CARRIER BUFFERING DEVICE AND STORAGE METHOD
The interference between overhead travelling vehicles and a local vehicle is prevented, in a situation where an overhead travelling vehicle has trouble, and...
2017/0200624 SUBSTRATE PROCESSING APPARATUS AND METHOD OF CLEANING SUBSTRATE PROCESSING APPARATUS
Disclosed is a substrate processing apparatus including: a holding unit configured to hold a substrate; a processing liquid supply unit configured to supply a...
2017/0200623 CLEANING APPARATUS
A cleaning apparatus 1 is provided with a heating unit 5 that heats a cleaning surface of a substrate W, a cleaning unit 6 that supplies ozone water to the...
2017/0200622 VACUUM EVACUATION SYSTEM
The present invention relates to a vacuum evacuation system used to evacuate a processing gas from one or more process chambers for use in, for example, a...
2017/0200621 NOVEL METHOD AND MATERIALS FOR WARPAGE THERMAL AND INTERCONNECT SOLUTIONS
Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top...
2017/0200620 IMPLANT AFTER THROUGH-SILICON VIA (TSV) ETCH TO GETTER MOBILE IONS
A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the...
2017/0200619 ANTI-REFLECTIVE COATING CLEANING AND POST-ETCH RESIDUE REMOVAL COMPOSITION HAVING METAL, DIELECTRIC AND NITRIDE...
A liquid removal composition and process for removing anti-reflective coating (ARC) material and/or post-etch residue from a substrate having same thereon. The...
2017/0200618 SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING SYSTEM
There is provided a substrate processing method which includes: treating a substrate using a fluorine-containing gas; and exposing the substrate to a...
2017/0200617 POLISHING LIQUID FOR CMP, POLISHING LIQUID SET FOR CMP, AND POLISHING METHOD
One embodiment of the present invention relates to a polishing liquid for CMP containing cerium oxide particles and water, wherein the half-value width of the...
2017/0200616 METHODS OF FABRICATING SEMICONDUCTOR DEVICES
A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area...
2017/0200615 ETCH RESISTANT ALUMINA BASED COATINGS
Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the...
2017/0200614 USING TENSILE MASK TO MINIMIZE BUCKLING IN SUBSTRATE
A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask...
2017/0200613 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the...
2017/0200612 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate. The...
2017/0200611 MANUFACTURING METHOD OF MEMORY DEVICE
A manufacturing method for a memory device includes forming a stack structure over a substrate, forming a mask pattern over the stack structure, forming a...
2017/0200610 PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC
Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an...
2017/0200609 METHODS OF FABRICATING A SEMICONDUCTOR DEVICE
Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then...
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