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Patent # Description
2017/0221911 FLASH MEMORY AND METHOD OF FABRICATING THE SAME
The flash memory includes a stacked gate disposed on a substrate. The stacked gate includes an erase gate and two floating gates. Each floating gate has an...
2017/0221910 ONE-TIME-PROGRAMMING (OTP) MEMORY CELL WITH FLOATING GATE SHIELDING
A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and...
2017/0221909 METHOD TO IMPROVE FLOATING GATE UNIFORMITY FOR NON-VOLATILE MEMORY DEVICE
The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a...
2017/0221908 METHOD AND STRUCTURE FOR FINFET SRAM
A method for forming a semiconductor device includes providing a substrate structure having a plurality of semiconductor fins disposed on a substrate and a...
2017/0221907 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a semiconductor device, a first FinFET including a first fin structure, a first gate electrode structure disposed over the first...
2017/0221906 Method for Semiconductor Device Fabrication with Improved Source Drain Proximity
A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate...
2017/0221905 SRAM CELL AND LOGIC CELL DESIGN
An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell...
2017/0221904 Two-Port SRAM Structure
An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a...
2017/0221903 METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a...
2017/0221902 METHOD AND SYSTEM FOR FORMING MEMORY FIN PATTERNS
Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and...
2017/0221901 METHODS OF FORMING BURIED VERTICAL CAPACITORS AND STRUCTURES FORMED THEREBY
Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such...
2017/0221900 Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to...
2017/0221899 Microcontroller System
An object is to provide a microcontroller (MCU) system with low power consumption. The MCU system includes a CPU, a first memory cell, and a second memory...
2017/0221898 HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE...
An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least...
2017/0221897 SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT STRUCTURE
A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions...
2017/0221896 DILUTED DRIFT LAYER WITH VARIABLE STRIPE WIDTHS FOR POWER TRANSISTORS
A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift...
2017/0221895 DIELECTRIC LINER ADDED AFTER CONTACT ETCH BEFORE SILICIDE FORMATION
A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon,...
2017/0221894 Field Effect Transistor Contact with Reduced Contact Resistance
The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate...
2017/0221893 INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME
An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate...
2017/0221892 METHOD TO IMPROVE DEVICE PERFORMANCE FOR FINFET
A method includes providing a semiconductor structure comprising multiple fins and a gate structure on the fins. The method also includes removing a portion of...
2017/0221891 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region...
2017/0221890 METHOD AND DEVICE OF PREVENTING MERGING OF RESIST-PROTECTION-OXIDE (RPO) BETWEEN ADJACENT STRUCTURES
A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding...
2017/0221889 GATE STACK FOR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING SAME
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a...
2017/0221888 METHOD OF FORMING SUPER STEEP RETROGRADE WELLS ON FINFET
A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing...
2017/0221887 BIPOLAR JUNCTION TRANSISTORS WITH EXTRINSIC DEVICE REGIONS FREE OF TRENCH ISOLATION
Device structures and fabrication methods for a device structure. One or more trench isolation regions are formed in a substrate to surround a device region. A...
2017/0221886 TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS
Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are...
2017/0221885 Electric Circuit Including a Semiconductor Device with a First Transistor, a Second Transistor and a Control...
An electric circuit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor in a common semiconductor...
2017/0221884 VERTICALLY STACKED NANOWIRE FIELD EFFECT TRANSISTORS
A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first...
2017/0221883 SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an...
2017/0221882 SWITCH IMPROVEMENT USING LAYOUT OPTIMIZATION
Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is...
2017/0221881 INSULATED GATE BIPOLAR TRANSISTOR (IGBT) AND RELATED METHODS
An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and...
2017/0221880 TUNABLE DEVICE HAVING A FET INTEGRATED WITH A BJT
A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET...
2017/0221879 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LEAKAGE CURRENT REDUCTION AND ASSOCIATED ELECTROSTATIC...
An electrostatic discharge (ESD) protection circuit has an ESD detection circuit, an ESD clamp circuit, and a leakage current reduction circuit. The ESD...
2017/0221878 SEMICONDUCTOR DEVICE HAVING ESD ELEMENT
When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors...
2017/0221877 SEMICONDUCTOR DEVICE AND CIRCUIT
The present disclosure relates to a semiconductor device. The semiconductor device includes a substrate, a first doping region, a second doping region, a third...
2017/0221876 ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE
An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate...
2017/0221875 DIODE DEVICE OF TRANSIENT VOLTAGE SUPPRESSOR AND MANUFACTURING METHOD THEREOF
A diode device of a transient voltage suppressor (TVS) is disclosed. The diode device includes a substrate, a first well, a second well, a first electrode and...
2017/0221874 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without...
2017/0221873 APPARATUSES AND METHODS FOR FORMING DIE STACKS
Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a...
2017/0221872 MANUFACTURE OF WAFER - PANEL DIE PACKAGE ASSEMBLY TECHNOLOGY
Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to ...
2017/0221871 SYSTEMS AND METHODS FOR MANUFACTURING ELECTRONIC DEVICES
Systems and processes for flexible and/or low volume product manufacture, including cost effective ways to manufacture low volume system level devices. In one...
2017/0221870 LIGHT EMITTING DEVICE PACKAGE
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom,...
2017/0221869 METHOD OF PRODUCING OPTOELECTRONIC COMPONENT WITH INTEGRATED PROTECTION DIODE
A method of producing an optoelectronic component includes providing an optoelectronic semiconductor chip having a first surface on which a first electrical...
2017/0221868 MANUFACTURING METHODS SEMICONDUCTOR PACKAGES INCLUDING THROUGH MOLD CONNECTORS
A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first...
2017/0221867 SEMICONDUCTOR DEVICE
A semiconductor device includes a wiring substrate including an upper surface on which a component pad and a connection pad are formed, an electronic component...
2017/0221866 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of...
2017/0221865 Packaging a Substrate with an LED into an Interconnect Structure Only Through Top Side Landing Pads on the...
Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass...
2017/0221864 LED PACKAGE
An LED module includes: a substrate including main, rear, and bottom surfaces; a first light emitting element disposed on the main surface; a conductive layer...
2017/0221863 Semiconductor Device and Method
A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor...
2017/0221862 COOLING SYSTEM FOR 3D IC
A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a...
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