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Patent # Description
2017/0221861 Method for Through Silicon via Structure
A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a...
2017/0221860 MULTI-CHIP PACKAGE STRUCTURE, WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF
A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of...
2017/0221858 Tri-Layer CoWoS Structure
A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package...
2017/0221857 Attaching chip attach medium to already encapsulated electronic chip
A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the...
2017/0221856 METHOD FOR BONDING SUBSTRATES TOGETHER, AND SUBSTRATE BONDING DEVICE
A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional...
2017/0221855 METAL PASTE AND USE THEREOF FOR THE CONNECTING OF COMPONENTS
A metal paste contains (A) 75% to 90% by weight of at least one metal that is present in the form of particles comprising a coating that contains, at least one...
2017/0221854 THERMOCOMPRESSION BONDING SYSTEMS AND METHODS OF OPERATING THE SAME
A thermocompression bonding system for bonding semiconductor elements is provided. The thermocompression bonding system includes (1) a bond head assembly...
2017/0221853 ELECTRODE TERMINAL, SEMICONDUCTOR DEVICE, AND POWER CONVERSION APPARATUS
An electrode terminal includes a body and a first bonding part. The body includes a first metal material. Then, the first bonding part is bonded to one end of...
2017/0221852 SINTERING TOOL FOR THE LOWER DIE OF A SINTERING DEVICE
Tool (10) for the lower die of a sintering device, the tool (10) having a rest (20) for an electronic subassembly (30) comprising a circuit carrier, to be...
2017/0221851 Laser-Induced Forming and Transfer of Shaped Metallic Interconnects
A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using...
2017/0221850 SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE
A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer...
2017/0221849 ENCAPSULATED ELECTRONIC DEVICE MOUNTED ON A REDISTRIBUTION LAYER
A substrateless device comprises a plurality of first conductive elements and an encapsulant. The encapsulant encapsulates the plurality of first conductive...
2017/0221848 CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING CIRCUIT SUBSTRATE
A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a...
2017/0221847 MICROELECTRONIC SUBSTRATE HAVING EMBEDDED TRACE LAYERS WITH INTEGRAL ATTACHMENT STRUCTURES
A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a...
2017/0221846 OPEN-PASSIVATION BALL GRID ARRAY PADS
A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive...
2017/0221845 Packaging Devices and Methods of Manufacture Thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad...
2017/0221844 SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS
A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically...
2017/0221843 Semiconductor Devices and Methods of Manufacture Thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor...
2017/0221842 POWER SEMICONDUCTOR DEVICE LOAD TERMINAL
A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device...
2017/0221841 METHOD FOR THERMO-MECHANICAL STRESS REDUCTION IN SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE
In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a...
2017/0221840 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE
In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having...
2017/0221839 STRUCTURE FOR RADIO-FREQUENCY APPLICATIONS
A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having...
2017/0221838 FAN-OUT PACKAGE STRUCTURE, ANTENNA SYSTEM AND ASSOCIATED METHOD
A fan-out package structure is disclosed. The fan-out package structure includes an antenna main body; a redistribution layer (RDL); and an antenna auxiliary...
2017/0221837 DICING CHANNELS FOR GLASS INTERPOSERS
The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and...
2017/0221836 SPUTTERING SYSTEMS AND METHODS FOR PACKAGING APPLICATIONS
Sputtering systems and methods for packaging applications. In some embodiments, a method for processing a plurality of packaged devices can include forming or...
2017/0221835 DOUBLE-SIDED PACKAGE MODULE AND SUBSTRATE STRIP
A double-sided package module includes a substrate, a first sealing member, a second sealing member, and an extension portion. The substrate includes...
2017/0221834 METHOD OF FORMING SEMICONDUCTOR STRUCTURE WITH ALIGNING MARK
The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central...
2017/0221833 MARK STRUCTURE AND FABRICATION METHOD THEREOF
The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a...
2017/0221832 SEMICONDUCTOR DEVICE INCLUDING AN OPTICAL MEASUREMENT PATTERN
A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip...
2017/0221831 INTERCONNECT STRUCTURE HAVING TUNGSTEN CONTACT COPPER WIRING
Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect...
2017/0221830 FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE
A method of making a semiconductor device can include providing a temporary carrier with a semiconductor die mounting site, and forming conductive...
2017/0221829 ELECTRONIC COMPONENT INTEGRATED SUBSTRATE
An electronic component integrated substrate includes a first substrate including a first pad, a first solder resist layer provided with a first open portion...
2017/0221828 BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY
Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package...
2017/0221827 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric...
2017/0221826 LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level...
2017/0221825 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated...
2017/0221824 SEMICONDUCTOR DEVICE
Provided is a semiconductor device preventing readhesion of conductive body which forms fuse elements and breakage of the fuse elements. The semiconductor...
2017/0221823 METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an...
2017/0221822 ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a...
2017/0221821 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a...
2017/0221820 Info Coil Structure and Methods of Manufacturing Same
A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material...
2017/0221819 Wireless Charging Package with Chip Integrated in Coil Center
A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with...
2017/0221818 LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND...
A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on...
2017/0221817 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE
A method of producing a semiconductor device, comprising the steps of forming a through hole in a semiconductor substrate having a first main surface, a second...
2017/0221816 Method and Apparatus for Back End of Line Semiconductor Device Processing
A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process...
2017/0221815 INTERCONNECT SCALING
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the...
2017/0221814 SEMICONDUCTOR DEVICE
A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side...
2017/0221813 INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that...
2017/0221812 INTERCONNECTION STRUCTURE AND METHOD OF FORMING THE SAME
An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present...
2017/0221811 Semiconductor Devices Having Nonlinear Bitline Structures
Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of...
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