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Patent # Description
2017/0221810 Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects
Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit...
2017/0221809 SEMICONDUCTOR APPARATUS
A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance...
2017/0221808 SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY
A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal...
2017/0221807 Circuit Board and Smart Card Module and Smart Card Utilizing the Same
A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region...
2017/0221806 Circuit Board and Smart Card Module and Smart Card Utilizing the Same
A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region...
2017/0221805 SEMICONDUCTOR PACKAGE DEVICE
An electronic device comprises a carrier, a leadframe, a package body and a plurality of electronic components. The carrier has an open top surface, a closed...
2017/0221804 RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE
Provided is a resin-encapsulated semiconductor device in which heat dissipation characteristic and mounting strength to a substrate are improved. Heat...
2017/0221803 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is...
2017/0221802 Semiconductor Device Packaging Assembly, Lead Frame Strip and Unit Lead Frame with Molding Compound Channels
A semiconductor device packaging assembly includes a lead frame strip having a plurality of unit lead frames. Each of the unit lead frames includes a periphery...
2017/0221801 Multi-Terminal Device Packaging
A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device...
2017/0221800 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having...
2017/0221799 PLANAR LEADFRAME SUBSTRATE HAVING A DOWNSET BELOW WITHIN A DIE AREA
A leadframe for encasing in a mold material includes a plurality of interconnected support members. A die pad is connected to the support members and includes...
2017/0221798 COMPACT MULTI-DIE POWER SEMICONDUCTOR PACKAGE
One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its...
2017/0221797 Integrated Circuit and Manufacturing and Method Thereof
A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second...
2017/0221796 THROUGH-SILICON VIA STRUCTURE
A TSV structure includes a substrate comprising at least a TSV opening formed therein, a conductive layer disposed in the TSV opening, and a bi-layered liner...
2017/0221795 THROUGH HOLE ARRAYS FOR FLEXIBLE LAYER INTERCONNECTS
Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical...
2017/0221794 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor structure includes a semiconductor substrate, a dielectric layer, a buffer layer, at least one recess, and at least one conductor. The...
2017/0221793 SINGLE BASE MULTI-FLOATING SURFACE COOLING SOLUTION
An apparatus including a primary device and at least one secondary device coupled to a substrate; a heat exchanger disposed on the primary device and on the at...
2017/0221792 DIRECT BONDED COPPER SEMICONDUCTOR PACKAGES AND RELATED METHODS
A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC...
2017/0221791 THERMAL INTERFACE MATERIAL (TIM) WITH THERMALLY CONDUCTIVE INTEGRATED RELEASE LAYER
A thermal interface material (TIM) includes a modified release layer having an organosilane-coated surface covalently bound to a TIM formulation layer. The...
2017/0221790 SEMICONDUCTOR PACKAGING STRUCTURE AND PACKAGE HAVING STRESS RELEASE STRUCTURE
A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim...
2017/0221789 BUMP STRUCTURE DESIGN FOR STRESS REDUCTION
Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die....
2017/0221788 Semiconductor Device and Method of Manufacture
A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral...
2017/0221787 UNDERFILL MATERIAL AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
An underfill material enabling voidless packaging and excellent solder bonding properties, and a method for manufacturing a semiconductor device using the same...
2017/0221786 Bonded Substrate, Method for Manufacturing the Same, and Support Substrate for Bonding
A method for manufacturing a bonded substrate is provided, the bonded substrate including a single-crystal semiconductor substrate on a sintered-body substrate...
2017/0221785 Power semiconductor module having a pressure application body and arrangement therewith
A power semiconductor module having a pressure application body, a circuit carrier, which is embodied with a first conductor track, a power semiconductor...
2017/0221784 TFT SWITCH AND METHOD FOR MANUFACTURING THE SAME
A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first...
2017/0221783 SELF-AWARE PRODUCTION WAFERS
Embodiments include a self-aware substrate and methods for utilizing a self-aware substrate. In one embodiment, a method of processing a self-aware substrate...
2017/0221782 SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method is provided. In a semiconductor wafer prepared, the width of a dicing line is larger than a cut region to be diced...
2017/0221781 SYSTEM AND METHOD OF DETERMINING PROCESS COMPLETION OF POST HEAT TREATMENT OF A DRY ETCH PROCESS
Provided is a method for determining and utilizing process completion of PHT (PHT) of a dry etch process, the method comprising: providing a substrate in a...
2017/0221780 PACKAGED WAFER PROCESSING METHOD
A packaged wafer processing method includes a processing step of processing each division line formed on a packaged wafer by using a laser beam applying unit...
2017/0221779 REDUCING DARK CURRENT IN GERMANIUM PHOTODIODES BY ELECTRICAL OVER-STRESS
Systems for reducing dark current in a photodiode include a heater configured to heat a photodiode above room temperature. A reverse bias voltage source is...
2017/0221778 NON-DESTRUCTIVE ACOUSTIC METROLOGY FOR VOID DETECTION
Advanced interconnect technologies such as Through Silicon Vias (TSVs) have become an integral part of 3-D integration. Methods and systems and provided for...
2017/0221777 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF FORMING MASK
A first mask with a first pattern is formed above a substrate, a first portion is formed in or above the substrate using the first mask, a second mask with a...
2017/0221776 METHOD AND APPARATUS FOR MEASURING SURFACE PROFILE
[Technical Problem] An object is to provide a method and apparatus for measuring a surface profile that enable correction or the like of the surface profile...
2017/0221775 REAL TIME PROCESS CHARACTERIZATION
Embodiments include process monitoring devices and methods of using such process monitoring devices. In one embodiment, the process monitoring device includes...
2017/0221774 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE CONTAINING HIGH MOBILITY SEMICONDUCTOR CHANNEL MATERIALS
A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an...
2017/0221773 METHOD AND STRUCTURE FOR ENABLING CONTROLLED SPACER RIE
A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin...
2017/0221772 System and Method for a Field-Effect Transistor with Dual Vertical Gates
A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first...
2017/0221771 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES BY FORMING SOURCE/DRAIN REGIONS BEFORE GATE ELECTRODE SEPARATION
Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode...
2017/0221770 Integrated Circuit Devices and Methods of Manufacturing the Same
An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer...
2017/0221769 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench...
2017/0221767 METHOD OF MANUFACTURING A DOPANT TRANSISTOR LOCATED VERTICALLY ON THE GATE
A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone...
2017/0221766 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with...
2017/0221765 SEMICONDUCTOR DEVICE AND FORMATION THEREOF
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane,...
2017/0221764 METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING
Methods to form multi V.sub.t channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed....
2017/0221763 METHOD OF PROCESSING A SUBSTRATE
The invention relates to a method of processing a substrate, having a first surface with a device area and a second surface opposite the first surface, wherein...
2017/0221762 ACTIVE MATRIX ORGANIC LIGHT EMITTING DIODE ARRAY SUBSTRATE, FABRICATING METHOD, AND DISPLAY APPARATUS
In some embodiments of the disclosed subject matter provides an active matrix organic light emitting diode array substrate, comprising; multiple pixel units in...
2017/0221761 3D SEMICONDUCTOR DEVICE AND SYSTEM
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second...
2017/0221760 Self-Alignment of Metal and Via Using Selective Deposition
Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully...
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