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Patent # Description
2017/0221557 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein...
2017/0221556 Programming Techniques for Non-Volatile Memories with Charge Trapping Layers
Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a...
2017/0221555 SRAM WITH STACKED BIT CELLS
Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter...
2017/0221554 SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF
A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain...
2017/0221553 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and...
2017/0221552 STATIC RANDOM ACCESS MEMORY (SRAM) TRACKING CELLS AND METHODS OF FORMING SAME
An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current...
2017/0221551 TIMED SENSE AMPLIFIER CIRCUITS AND METHODS IN A SEMICONDUCTOR MEMORY
A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable...
2017/0221550 STORAGE ELEMENT WITH MULTIPLE CLOCK CIRCUITS
Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to...
2017/0221549 SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device includes, a memory array, a plurality of memory cells provided in rows and columns, and a control circuit for controlling the...
2017/0221548 SRAM ARRAYS AND METHODS OF MANUFACTURING SAME
An embodiment static random access memory (SRAM) array includes a first SRAM mini array having a first plurality of functional SRAM cells in a first column of...
2017/0221547 Method for Operating the Semiconductor Device
A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger...
2017/0221546 VOLATILE MEMORY DEVICE AND ELECTRONIC DEVICE COMPRISING REFRESH INFORMATION GENERATOR, INFORMATION PROVIDING...
A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a...
2017/0221545 MEMORY DEVICE AND SYSTEM INCLUDING THE SAME
A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when...
2017/0221544 MEMORY INTERFACE CIRCUIT HAVING SIGNAL DETECTOR FOR DETECTING CLOCK SIGNAL
A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock...
2017/0221543 SEMICONDUCTOR MEMORY DEVICE INCLUDING POWER DECOUPLING CAPACITOR
A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The...
2017/0221542 CELL-BASED REFERENCE VOLTAGE GENERATION
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first...
2017/0221541 MAGNETIC MEMORY DEVICE AND OPERATING METHOD THEREOF
A magnetic memory device may include a bit line, a plurality of source lines, a plurality of normal cells coupled between the bit line and the plurality of...
2017/0221540 METHOD FOR CONTROLLED SWITCHING OF A MRAM DEVICE
A method and apparatus for controlled switching of a magnetoresistive random access memory device is disclosed herein. The method includes delivering a current...
2017/0221539 ELECTRONIC DEVICE
An electronic device including an inverter includes a pull-up driving unit configured to drive an output node with a high voltage in response to an input...
2017/0221538 SEMICONDUCTOR DEVICES HAVING SEPARATE SOURCE LINE STRUCTURE
A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a...
2017/0221537 HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME
Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant...
2017/0221536 METHODS AND APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS
Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a...
2017/0221535 NON-VOLATILE MEMORY ACCELERATOR AND METHOD FOR SPEEDING UP DATA ACCESS
A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit,...
2017/0221534 SEMICONDUCTOR MEMORY PACKAGE
A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal...
2017/0221533 DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS
An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second...
2017/0221532 SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP
Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an...
2017/0221531 REFERENCE CURRENT GENERATING CIRCUIT AND MEMORY DEVICE
A reference current generating circuit includes a positive temperature coefficient current source configured to generate a first current, a value of which...
2017/0221530 COMPUTERIZED DEVICE FOR THE MARGINAL STATE ASSESSMENT OF POWER SYSTEMS
The required technical result aimed to raise a speed of device response is achieved in the device, which includes a group of operative memory blocks, a data...
2017/0221529 Compact Three-Dimensional Memory with an Above-Substrate Decoding Stage
The above-substrate decoding stage of a compact three-dimensional memory (3D-M.sub.c) could be an intra-level decoding stage, an inter-level decoding stage, or...
2017/0221528 Compact Three-Dimensional Memory with Semi-Conductive Address Line Portion
In a compact three-dimensional memory (3D-M.sub.C), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the...
2017/0221527 Adhesive Leak Channel Structure For Hermetic Sealing Of A Hard Disk Drive
In the context of a hard disk drive (HDD), an adhesive leak channel structural feature is positioned in an area at which an electrical feed-through is adhered...
2017/0221526 ACOUSTIC ATTENUATION IN DATA STORAGE ENCLOSURES
To provide enhanced operation of data storage devices and systems, various systems and apparatuses are provided herein. In a first example, a data storage...
2017/0221525 Clip Scheduling with Conflict Alert
An example method involves: accessing a first list including ordered clip identifiers C.sub.1 . . . C.sub.n; accessing a second list including ordered player...
2017/0221524 INFORMATION PROCESSING APPARATUS, INFORMATION RECORDING MEDIUM, AND INFORMATION PROCESSING METHOD, AND PROGRAM
To acquire attribute information of high dynamic range (HDR) data from a playlist file and a clip information file to realize video reproduction according to a...
2017/0221523 ANNOTATING MEDIA CONTENT FOR AUTOMATIC CONTENT UNDERSTANDING
A system for annotating frames in a media stream 114 includes a pattern recognition system (PRS) 108 to generate PRS output metadata for a frame; an archive...
2017/0221522 SYSTEMS AND METHODS FOR GENERATION OF COMPOSITE VIDEO
Systems and methods for generating a composite video based on a plurality of input streams are provided. A first video stream is received from a first device....
2017/0221521 Distinguishing HEVC Pictures for Trick Mode Operations
Assistance information related to a tier framework may describe signaling for extractable and decodable sub-sequences based on pictures interdependencies. This...
2017/0221520 SYSTEMS AND METHODS TO PLAY SECONDARY MEDIA CONTENT
Systems and methods to play secondary media content include responding to a trick mode request (e.g., fast forward, rewind). A system receives a message from a...
2017/0221519 REWRITING OF DATA STORED IN DEFECTIVE STORAGE REGIONS INTO OTHER STORAGE REGIONS
A storage apparatus includes a storage disk including a plurality of tracks each of which includes a plurality of sectors, a head configured to write data in...
2017/0221518 OPTICAL INFORMATION RECORDING MEDIUM HAVING FIRST AND SECOND PIT ROW OF IDENTICAL REFLECTANCE
In a case where (i) a reflectance calculated from a reflected light amount obtained from a longest pit (P1max) or a longest space (S1max) in a first pit row is...
2017/0221517 MAGNETIC TAPE AND METHOD OF MANUFACTURING THE SAME
The magnetic tape has a magnetic layer and a backcoat layer, wherein, each of the magnetic layer and backcoat layer contains a fatty acid ester, the Ra...
2017/0221516 MAGNETIC TAPE AND METHOD OF MANUFACTURING THE SAME
The magnetic tape has a magnetic layer and a backcoat layer, wherein the Ra on the magnetic layer side surface is less than or equal to 1.8 nm, the coefficient...
2017/0221515 MAGNETIC RECORDING MEDIUM AND MAGNETIC RECORDING AND REPRODUCING APPARATUS
A magnetic recording medium includes a non-magnetic substrate on which at least a soft magnetic underlayer, an orientation control layer, a perpendicular...
2017/0221514 TAPE RECORDING MEDIUM
In a tape recording medium, a sliding layer has an electric resistance of 1.times.10.sup.8 .OMEGA./sq or less, and contains carbon particles and solid...
2017/0221513 MAGNETIC RECORDING MEDIUM
A magnetic recording medium of the present invention includes a non-magnetic substrate, and a magnetic layer containing a magnetic powder. The magnetic powder...
2017/0221512 HARD DISK DRIVE, MANUFACTURING METHOD OF THE SAME, AND SERVO DATA WRITING METHOD
A method for writing servo data includes writing servo data as a head moves outward on a disk one step at a time, so as to overwrite part of servo data that...
2017/0221511 REDUCING CARBONACEOUS SMEAR AT THE NFT AREA ON HAMR HEAD
The present disclosure generally relates a method for removing a smear from a write head in a HAMR system. The smear can be removed by sufficiently heating the...
2017/0221510 DATA READER WITH FRONT SHIELD COUPLING STRUCTURE
A data reader may consist of at least a magnetoresistive stack positioned on an air bearing surface. A portion of the magnetoresistive stack may be set to a...
2017/0221509 TUNNEL MAGNETORESISTIVE SENSOR HAVING CONDUCTIVE CERAMIC LAYERS
An apparatus according to one embodiment includes a sensor having an active region, a magnetic shield adjacent the active region, and a spacer between the...
2017/0221508 L1o-Ordered MnAl Thin Films with High Perpendicular Magnetic Anisotropy, and Structures and Devices Made Therewith
A stacked-thin-film structure that includes an Llo-ordered MnAl layer having high perpendicular magnetic anisotropy (PMA). In some embodiments, the Ll0-ordered...
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