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Patent # Description
2017/0229500 IMAGE SENSOR, IMAGE PROCESSING SYSTEM INCLUDING THE SAME, AND PORTABLE ELECTRONIC DEVICE INCLUDING THE SAME
An image sensor includes a first pixel that is in an active pixel region, a second pixel that is in a dummy region adjacent the active pixel region, and a...
2017/0229499 IMAGE SENSORS WITH ADJUSTABLE PIXEL DENSITY AND PIXEL DENSITY ADJUSTMENT METHODS THEREOF
Embodiments of the present application disclose image sensors with adjustable pixel density and pixel density adjustment methods thereof, wherein one of the...
2017/0229498 SOLID-STATE IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
A solid-state image sensor is provided. The sensor includes a first transistor including a first diffusion region, a second transistor including a second...
2017/0229497 BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
A backside illuminated image sensor includes a substrate having a frontside surface and a backside surface, a photodiode disposed in the substrate, an...
2017/0229496 PIXELS FOR HIGH PERFORMANCE IMAGE SENSOR
Visual and near infrared pixels may have deep photodiodes to ensure sufficient capture of light. The pixels may have a silicon layer that is etched to form a...
2017/0229495 Image Pickup Device and Method of Manufacturing the Same
A P-type well is defined by an isolation region formed in a semiconductor substrate. A pixel region and a ground region are defined in the P-type well. In the...
2017/0229494 VOLTAGE BIASED METAL SHIELDING AND DEEP TRENCH ISOLATION FOR BACKSIDE ILLUMINATED (BSI) IMAGE SENSORS
A backside illuminated (BSI) image sensor for biased backside deep trench isolation (BDTI) and/or biased backside shielding is provided. A photodetector is...
2017/0229493 PIXEL CIRCUIT AND IMAGING APPARATUS
Dark current of FD is eliminated in an image sensor, and conversion efficiency of converting electric charge to voltage is improved. A pixel circuit includes a...
2017/0229492 MASK PLATE AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE
The present disclosure provides a mask plate, including a first region corresponding to a GOA region of an array substrate and a second region corresponding to...
2017/0229491 DISPLAY AND MANUFACTURE METHOD THEREOF
A display includes a first substrate, a second substrate, a plurality of pixels and a photo-catalyst layer. The plurality of pixels are disposed between the...
2017/0229490 INTERFACE ENGINEERING FOR HIGH CAPACITANCE CAPACITOR FOR LIQUID CRYSTAL DISPLAY
Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for...
2017/0229488 DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE DISPLAY DEVICE
To provide a display device including a transistor that includes an oxide semiconductor and has favorable characteristics, a pixel electrode electrically...
2017/0229487 LIQUID CRYSTAL DISPLAY DEVICE WITH OXIDE THIN FILM TRANSISTOR
A method of making a display device includes, providing a substrate having a display area and a pad area in a periphery of the display area, the display area...
2017/0229486 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
To provide a semiconductor device capable of retaining data for a long period. The semiconductor device includes a memory circuit and a retention circuit. The...
2017/0229485 SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPLIANCE
In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable...
2017/0229484 DISPLAY DEVICE
A display device is provided. The display device includes a display region, a first conductive loop disposed outside the display region, wherein the first...
2017/0229483 PIXEL STRUCTURE AND FABRICATING METHOD THEREOF
A pixel structure includes a scan line, a data line, a bump, an active device, and a pixel electrode electrically connected to the active device. The active...
2017/0229482 SELF-EMISSION TYPE DISPLAY
A self-emission type display including a carrier substrate, a light-emitting element, a first electrode, and a second electrode is provided. The light-emitting...
2017/0229481 PANEL STRUCTURES OF FLAT DISPLAYS AND MANUFACTURING METHODS
The present disclosure discloses a panel structure of flat displays and the manufacturing method thereof. The panel structure includes a first signal line, a...
2017/0229480 SEMICONDUCTOR DEVICE INCLUDING A HIGH-ELECTRON-MOBILITY TRANSISTOR (HEMT) AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device comprises a substrate and a high-electron-mobility transistor (HEMT). The substrate is formed with a recess. At least a portion of the...
2017/0229479 INTEGRATED CIRCUIT (IC) WITH OFFSET GATE SIDEWALL CONTACTS AND METHOD OF MANUFACTURE
A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates...
2017/0229478 SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs...
2017/0229476 NON-VOLATILE MEMORY DEVICE
A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends ...
2017/0229475 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, and a charge storage film. The stacked...
2017/0229474 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor memory device according to one embodiment includes a stacked body, a semiconductor pillar and a plurality of charge storage films. The stacked...
2017/0229473 SEMICONDUCTOR MEMORY DEVICE HAVING VOIDS BETWEEN WORD LINES AND A SOURCE LINE
According to an embodiment, a semiconductor memory device includes first and second stacked bodies, first and second memory parts, and an insulating part. The...
2017/0229472 MULTI-TIER REPLACEMENT MEMORY STACK STRUCTURE INTEGRATION SCHEME
A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and...
2017/0229471 SINGLE POLY NONVOLATILE MEMORY CELLS, ARRAYS THEREOF, AND METHODS OF OPERATING THE SAME
A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a...
2017/0229470 Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive...
2017/0229469 Semiconductor Device
A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile...
2017/0229468 STATIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF
An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down...
2017/0229467 Embedded Transistor
An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate...
2017/0229466 Memory Cell Comprising First and Second Transistors and Methods of Operating
Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an...
2017/0229465 METHODS AND SYSTEMS FOR REDUCING ELECTRICAL DISTURB EFFECTS BETWEEN THYRISTOR MEMORY CELLS USING BURIED METAL...
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between...
2017/0229464 METHODS AND SYSTEMS FOR REDUCING ELECTRICAL DISTURB EFFECTS BETWEEN THYRISTOR MEMORY CELLS USING...
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between...
2017/0229463 SINGLE SPACER FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PROCESS FLOW
A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device...
2017/0229461 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure...
2017/0229460 Fabricating a Dual Gate Stack of a CMOS Structure
A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel...
2017/0229459 III-V SEMICONDUCTOR CMOS FINFET DEVICE
A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form...
2017/0229458 THIRD TYPE OF METAL GATE STACK FOR CMOS DEVICES
A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement...
2017/0229457 SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of...
2017/0229456 INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY
Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a...
2017/0229455 MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in...
2017/0229454 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a...
2017/0229453 III-V FINS BY ASPECT RATIO TRAPPING AND SELF-ALIGNED ETCH TO REMOVE ROUGH EPITAXY SURFACE
A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are...
2017/0229452 FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME
Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, a first gate,...
2017/0229450 FIELD EFFECT TRANSISTORS
A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second...
2017/0229449 VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES
Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold...
2017/0229448 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
To provide a semiconductor device with a high degree of flatness, provided is a semiconductor device including a semiconductor substrate; an element insulating...
2017/0229447 COMPACT ESD BOOTSTRAP CLAMP
An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a...
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