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Patent # Description
2017/0236830 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELLS ARRANGED THREE-DIMENSIONALLY AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device includes a substrate, a plurality of insulating layers and wiring layers that are alternately formed, and a plurality of first...
2017/0236829 SINGLE-POLY NONVOLATILE MEMORY CELLS
A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a...
2017/0236828 Memory Cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
2017/0236827 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor memory device according to one embodiment includes a substrate, a stacked body provided on a first-direction side of the substrate, a...
2017/0236826 INTEGRATED CIRCUIT DEVICES AND FABRICATION TECHNIQUES
Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from...
2017/0236825 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH RESERVOIR CAPACITORS AND METHOD OF MANUFACTURING THE SAME
A semiconductor integrated circuit device may include a semiconductor chip, a power line region and a reservoir capacitor. The semiconductor chip may include a...
2017/0236824 COMPLEMENTARY BIPOLAR SRAM
A method of forming a complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a...
2017/0236823 SEMICONDUCTOR DEVICE
A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a...
2017/0236822 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second...
2017/0236821 SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS WITH ADJUSTED THRESHOLD VOLTAGES
A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region. First and second dielectric...
2017/0236820 SEMICONDUCTOR DEVICE, AND ON-VEHICLE ELECTRONIC DEVICE AND AUTOMOBILE EACH INCLUDING THE SEMICONDUCTOR DEVICE
A semiconductor integrated power device including: an output transistor configured to drive an external load element; a temperature detection circuit...
2017/0236819 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
A semiconductor device 100 includes a semiconductor element 12 having an electrode on a front surface, a wire 15 bonded to the electrode of the semiconductor...
2017/0236818 SEMICONDUCTOR DEVICE
A p-type well is formed in a semiconductor substrate, and an n.sup.+-type semiconductor region and a p.sup.+-type semiconductor region are formed in the p-type...
2017/0236817 ESD PROTECTION DEVICE
An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first...
2017/0236815 SYSTEM, APPARATUS, AND METHOD FOR N/P TUNING IN A FIN-FET
The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In...
2017/0236814 INTEGRATED CIRCUIT AND COMPUTER-IMPLEMENTED METHOD OF MANUFACTURING THE SAME
A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit,...
2017/0236813 Packaging Mechanisms for Dies With Different Sizes of Connectors
Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical...
2017/0236812 METHOD FOR MANUFACTURING POWER MODULE
A power module includes one control IC and a plurality of reverse conducting insulated gate bipolar transistors (RC-IGBTs). The control IC has the functions of...
2017/0236811 METHOD OF SELECTIVELY TRANSFERRING LED DIE TO A BACKPLANE USING HEIGHT CONTROLLED BONDING STRUCTURES
Selective transfer of dies including semiconductor devices to a target substrate can be performed employing local laser irradiation. Coining of at least one...
2017/0236810 ELECTRONIC DEVICE
In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an...
2017/0236809 CHIP PACKAGE ASSEMBLY WITH POWER MANAGEMENT INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT DIE
A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In...
2017/0236808 SEMICONDUCTOR PACKAGE WITH LID HAVING LID CONDUCTIVE STRUCTURE
The present disclosure relates to a semiconductor package with a lid that includes a lid conductive structure. The semiconductor package includes a substrate...
2017/0236807 III-V MICRO-LED ARRAYS AND METHODS FOR PREPARING THE SAME
III-V micro light-emitting diodes (LEDs) are fabricated using a photoelectrochemical (PEC) etch. A sacrificial layer and III-V device layers are epitaxially...
2017/0236806 LIGHT EMITTING APPARATUS, ILLUMINATION APPARATUS AND DISPLAY APPARATUS
A light emitting apparatus including: one or a plurality of light emitting devices each having a plurality of electrodes and each emitting light from the upper...
2017/0236805 Flexible Display Apparatus and Methods
A flexible display includes a plurality of pixel chips, chixels, provided on a flexible substrate. The chixels and the light emitters thereon may be shaped,...
2017/0236804 APPARATUSES AND METHODS FOR INTERNAL HEAT SPREADING FOR PACKAGED SEMICONDUCTOR DIE
Apparatuses and methods for internal heat spreading for packaged semiconductor die are disclosed herein. An example apparatus may include a plurality of die in...
2017/0236803 INTEGRATED CIRCUIT DIES WITH THROUGH-DIE VIAS
Aspects of the disclosure are directed to integrated circuit dies and their manufacture. In accordance with one or more embodiments, a plurality of integrated...
2017/0236802 Semiconductor Device and Method of Making Wafer Level Chip Scale Package
A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer...
2017/0236801 SEMICONDUCTOR DEVICES AND PROCESSING METHODS
Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed...
2017/0236800 METHOD FOR DIRECT ADHESION VIA LOW-ROUGHNESS METAL LAYERS
A method for assembling a first substrate and a second substrate via metal adhesion layers, the method including: depositing, on a surface of each of the first...
2017/0236799 BONDING METHOD FOR CONNECTING TWO WAFERS
The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a...
2017/0236798 APPARATUS FOR STACKING SEMICONDUCTOR CHIPS IN A SEMICONDUCTOR PACKAGE
An apparatus for stacking semiconductor chips includes a push member configured to apply pressure to a semiconductor chip disposed on a substrate. The push...
2017/0236797 Ball Height Control in Bonding Process
A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package...
2017/0236796 BUMP-EQUIPPED ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING BUMP-EQUIPPED ELECTRONIC COMPONENT
A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate...
2017/0236795 CONNECTION BODY
Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched...
2017/0236794 Multichip modules and methods of fabrication
In a multi-chip module (MCM), a "super" chip (110N) is attached to multiple "plain" chips (110F' "super" and "plain" chips can be any chips). The super chip is...
2017/0236793 Semiconductor Device
A semiconductor device according to an embodiment comprises a substrate, an epitaxial layer on the substrate, and a cluster including a plurality of particles...
2017/0236792 RELIABLE PASSIVATION FOR INTEGRATED CIRCUITS
Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is...
2017/0236791 INTEGRATED CIRCUIT DEVICE
The instant disclosure provides an integrated circuit device including a transmission line which includes a first ground line and a signal line. The first...
2017/0236790 Semiconductor Device on Leadframe with Integrated Passive Component
A semiconductor device includes a substrate and a first conductive layer formed over a first surface of the substrate. The first conductive layer is patterned...
2017/0236789 SEMICONDUCTOR DEVICE
A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest...
2017/0236788 Semiconductor Device and Method of Forming Interconnect Substrate for FO-WLCSP
A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to...
2017/0236787 METHOD OF FABRICATING SEMICONDUCTOR PACKAGE HAVING METAL LAYER
A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and...
2017/0236786 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate having a first surface, a second surface opposite the first surface, and interconnect patterns disposed therein, a...
2017/0236785 SHIELDED LEAD FRAME PACKAGES
Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, A radio-frequency...
2017/0236784 ION FLOW BARRIER STRUCTURE FOR INTERCONNECT METALLIZATION
A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a...
2017/0236783 PACKAGE STRUCTURE
The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming...
2017/0236782 SEMICONDUCTOR MODULE MANUFACTURING METHOD AND SEMICONDUCTOR MODULE
A semiconductor module manufacturing method, including preparing an external terminal that is of a pin shape and that has an outflow prevention portion formed...
2017/0236781 SELF-FORMING BARRIER FOR COBALT INTERCONNECTS
An interconnect for a semiconductor device includes an insulator layer having a trench. A barrier layer is formed on a surface of the insulator layer in the...
2017/0236780 INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME
An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a...
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