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Patent # Description
2017/0236779 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
According to one embodiment, a semiconductor memory device includes, a first interconnect layer provided on a first insulating layer and including a first...
2017/0236778 DEVICE WITH INTERCONNECTION STRUCTURE FOR FORMING A CONDUCTION PATH OR A CONDUCTING PLANE WITH HIGH DECOUPLING...
Electronic device comprising an interconnection structure comprising an alternating stack of arrays of conducting lines and dielectric layers in which: all...
2017/0236777 METHOD FOR MANUFACTURING A CIRCUIT CARRIER AND CIRCUIT CARRIER FOR ELECTRONIC COMPONENTS
A method for manufacturing a circuit carrier for electronic components includes making available a carrier material layer made of an electrically insulating...
2017/0236776 SEMICONDUCTOR DEVICE INCLUDING AN ANTENNA
A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is...
2017/0236775 LEAD FRAME AND METHOD FOR MANUFACTURING THE SAME
A metal plate 1 to be a lead frame has a plating with Sn or Zn or a plating with various alloys containing these metals only on the side faces and half-etched...
2017/0236774 SEMICONDUCTOR MODULE AND SEMICONDUCTOR DRIVING DEVICE
A semiconductor module forming a semiconductor device includes lead frames in which switching elements are mounted on the side of upper surfaces and heat...
2017/0236773 DEVICE WITH TOP-SIDE BASE PLATE
A device includes an integrated circuit (IC) die, a top-side base plate to which the IC die is mounted, and a body attached to the top-side base plate such...
2017/0236772 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has amounting portion which includes an...
2017/0236771 Method of Forming a Reliable and Robust Electrical Contact
In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active...
2017/0236770 COMPLIANT PIN FIN HEAT SINK AND METHODS
A heat sink includes a plurality of layers being disposed substantially parallel with a surface of a heat source. The layers include a plurality of pin...
2017/0236769 HIGH THERMAL CONDUCTIVE HERMETIC RF PACKAGING
A thermal packaging device for dissipating heat generated by electronic components comprising a copper base and a ceramic frame mounted to the base with a...
2017/0236768 HEAT-DISSIPATING STRUCTURE AND SEMICONDUCTOR MODULE USING SAME
A heat-dissipating structure is formed by bonding a first member and a second member, each being any of a metal, ceramic, and semiconductor, via a die bonding...
2017/0236767 ALUMINUM-SILICON CARBIDE COMPOSITE AND PRODUCTION METHOD THEREFOR
An aluminum-silicon carbide composite including flat-plate-shaped composited portion containing silicon carbide and an aluminum alloy, and aluminum layers...
2017/0236765 CHIP PART AND METHOD FOR MANUFACTURING A CHIP PART
A chip part includes a substrate that has an upper surface, a lower surface positioned on an opposite side of the upper surface, and a sidewall by which the...
2017/0236764 ELECTRONIC DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF
An electronic device package and a manufacturing method thereof are provided. The electronic device package includes a flexible substrate, a first wiring...
2017/0236763 POP Structures with Dams Encircling Air Gaps and Methods for Forming the Same
A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides...
2017/0236762 SEMICONDUCTOR DEVICE
Disclosed is a semiconductor device that is configured to contain a sealing layer for sealing a semiconductor element supported on a base, the sealing layer...
2017/0236761 HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING
Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an...
2017/0236760 LIGHT-EMITTING DIODE LIGHTING DEVICE AND METHOD FOR REPAIRING THE SAME
A method for repairing a light-emitting diode (LED) lighting device is provided. The method includes the operations below. First, the LED lighting device is...
2017/0236759 DUAL WORK FUNCTION CMOS DEVICES
A method for forming a semiconductor device includes forming a first channel region and a second channel region on a substrate, depositing a dielectric...
2017/0236758 MOSFET DEVICES WITH ASYMMETRIC STRUCTURAL CONFIGURATIONS INTRODUCING DIFFERENT ELECTRICAL CHARACTERISTICS
First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a...
2017/0236757 PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY
Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical...
2017/0236756 UNIFORM DIELECTRIC RECESS DEPTH DURING FIN REVEAL
A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag...
2017/0236755 TUNNELING FIN TYPE FIELD EFFECT TRANSISTOR WITH EPITAXIAL SOURCE AND DRAIN REGIONS
A method of forming semiconductor devices may begin with forming gate structures over fin structures on sidewalls of at least two mandrels. The mandrels are...
2017/0236754 Integrated Clip and Lead and Method of Making a Circuit
A circuit includes a conductive clip coupled to at least one component in the circuit. At least one lead portion is located on an end of the clip. The circuit...
2017/0236753 PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE
An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the...
2017/0236752 INTEGRATION OF A SELF-FORMING BARRIER LAYER AND A RUTHENIUM METAL LINER IN COPPER METALLIZATION
Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several...
2017/0236751 METHODS OF FORMING WIRING STRUCTURES FOR SEMICONDUCTOR DEVICES
A method of fabricating a wiring structure for a semiconductor device may include forming a lower wiring in a lower insulating layer, forming an etch stop...
2017/0236750 Method for Via Plating with Seed Layer
Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening...
2017/0236749 SELF-FORMING BARRIER FOR COBALT INTERCONNECTS
A method for forming a conductor includes forming trenches in an insulator layer. An alloy layer is deposited in the trenches. The alloy layer includes a...
2017/0236748 ION FLOW BARRIER STRUCTURE FOR INTERCONNECT METALLIZATION
A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a...
2017/0236747 SEMICONDUCTOR PROCESS FOR FORMING PLUG
A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is...
2017/0236746 MULTI-TIER MEMORY DEVICE WITH THROUGH-STACK PERIPHERAL CONTACT VIA STRUCTURES AND METHOD OF MAKING THEREOF
Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing...
2017/0236745 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS
A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed...
2017/0236744 Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid...
2017/0236743 WAFER LIFT RING SYSTEM FOR WAFER TRANSFER
A substrate support includes an inner portion arranged to support a substrate, a lift ring surrounding the inner portion, the lift ring arranged to support an...
2017/0236742 DEVICE PACKAGING USING A RECYCLABLE CARRIER SUBSTRATE
According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method...
2017/0236741 VARIABLE DEPTH EDGE RING FOR ETCH UNIFORMITY CONTROL
A substrate support includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller that calculates a...
2017/0236740 PATTERNED CHUCK FOR SUBSTRATE PROCESSING
A chuck for wafer processing that counters the deleterious effects of thermal expansion of the wafer. Also, a combination of chuck and shadow mask arrangement...
2017/0236739 HIGH SPEED SUBSTRATE ALIGNER APPARATUS
A substrate aligner providing minimal substrate transporter extend and retract motions to quickly align substrate without back side damage while increasing the...
2017/0236738 METHOD AND DEVICE FOR GROOVING WAFERS
A wafer grooving apparatus (100) for forming an elongate recess (103) in a semiconductor wafer surface, the apparatus comprising: a wafer table (110) for receiving...
2017/0236737 WAFER CONTAINER WITH DOOR GUIDE AND SEAL
A wafer container that reduces or alleviates one or more of the problems associated with excessive container wall deflection due to loading and excessive...
2017/0236736 DETECTION CIRCUIT, ELECTROSTATIC HOLDING DEVICE AND METHOD FOR DETECTING A COMPONENT ON AN ELECTROSTATIC...
Detection circuit for detecting electrical capacitance of electrode device in electrostatic holding device with clamp carrier, particularly for detecting...
2017/0236735 Line Charge Volume With Integrated Pressure Measurement
A line charge volume and methods for use in delivery of gas to a reactor for processing semiconductor wafers is provided. The line charge volume includes a...
2017/0236734 PICK AND PLACE DEVICE COMPRISING PICK ARM CORRECTION MODULE
A semiconductor die pick and place device comprising a handing mechanism comprising a pick arm movable between a placement location and a pick-up location. A...
2017/0236733 Common Terminal Heater for Ceramic Pedestals Used in Semiconductor Fabrication
System and methods for processing a substrate using a reactor with multiple heating zones and control of said heating zones using a common terminal shared...
2017/0236732 HIGH DEFINITION HEATER SYSTEM HAVING A FLUID MEDIUM
A thermal system includes a base member, a two-phase fluid, a tuning heater, and a chuck. The base member includes at least one fluid passageway. The two-phase...
2017/0236731 SYSTEMS AND METHODS FOR SELECTIVELY ETCHING FILM
A method for selectively etching one exposed material of a substrate relative to another exposed material of the substrate includes a) arranging the substrate...
2017/0236730 SUBSTRATE CLEANING APPARATUS AND SUBSTRATE PROCESSING APPARATUS
A substrate cleaning apparatus comprises: a cleaning member 11,21 that comes into contact with a substrate W and cleans the substrate W; a member rotating unit...
2017/0236729 LIQUID PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM
Disclosed is a liquid processing method of drying a substrate held horizontally after supplying deionized water to the substrate. The liquid processing method...
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