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Patent # Description
2017/0250216 IMAGING DEVICE
An imaging device includes a unit pixel cell including: a semiconductor substrate including a first region exposed to a surface of the semiconductor substrate...
2017/0250215 PAD STRUCTURE EXPOSED IN AN OPENING THROUGH MULTIPLE DIELECTRIC LAYERS IN BSI IMAGE SENSOR CHIPS
An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into...
2017/0250214 IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
In manufacturing an image sensor for FPD having an oxide semiconductor TFT as a switching element, a large amount of hydrogen contained in raw gas is diffused...
2017/0250213 IMAGING ELEMENT, METHOD FOR MANUFACTURING IMAGING ELEMENT, PIXEL DESIGN METHOD, AND ELECTRONIC APPARATUS
An imaging element includes a plurality of pixels that are two-dimensionally arranged and each have a light receiving part including a photoelectric conversion...
2017/0250212 ISOLATION STRUCTURE AND IMAGE SENSOR HAVING THE SAME
Disclosed is an image sensor having an isolation structure. The isolation structure includes a deep well region of a first conductive type disposed in a...
2017/0250211 SEMICONDUCTOR IMAGE SENSOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Semiconductor image sensor devices and manufacturing method of the same are disclosed. The semiconductor image sensor device includes a substrate, a first...
2017/0250210 SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS
Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a...
2017/0250209 Article Comprising a Photodiode-side Integrated Fuse for Avalanche Photodetector Focal Plane Array Pixels and...
A scalable fuse design for individual pixels of a focal plane array of photodiodes comprises a fuse disposed on the upper surface of each photodiode in the...
2017/0250208 MASK FOR DEPOSITION, APPARATUS FOR MANUFACTURING DISPLAY APPARATUS HAVING THE SAME, AND METHOD OF MANUFACTURING...
A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition...
2017/0250207 THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY APPARATUS
A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation...
2017/0250206 COMPOSITION FOR FORMING SILICA LAYER, METHOD FOR MANUFACTURING SILICA LAYER, AND SILICA LAYER
A composition for forming a silica layer, a method for manufacturing a silica layer, a silica layer manufactured by the method, and an electronic device...
2017/0250205 SEMICONDUCTOR DEVICE
An object of the present invention is to provide a semiconductor device in which stored data can be held even when power is not supplied for a certain time....
2017/0250204 SEMICONDUCTOR DEVICE
Stable electrical characteristics of a transistor including an oxide semiconductor layer are achieved. A highly reliable semiconductor device including the...
2017/0250203 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode...
2017/0250202 ARRAY SUBSTRATE FOR DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed...
2017/0250201 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor...
2017/0250200 TRANSISTOR LAYOUT WITH LOW ASPECT RATIO
A radio-frequency (RF) device includes a semiconductor substrate, a first field-effect transistor (FET) disposed on the substrate, the first FET having a first...
2017/0250199 DISPLAY DEVICE
A display device in an embodiment according to the present invention includes a substrate, a pixel part including a circuit element over the substrate, and a...
2017/0250198 METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE...
A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the...
2017/0250197 LAYOUT STRUCTURE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
In a circuit block, a plurality of standard cells are arranged to form a circuit of silicon-on-insulator (SOI) transistors. Also arranged in the circuit block...
2017/0250196 MULTI-LEVEL FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor...
2017/0250195 STACKED MEMORY DEVICE, OPTICAL PROXIMITY CORRECTION (OPC) VERIFYING METHOD, METHOD OF DESIGNING LAYOUT OF...
An optical proximity correction (OPC) verifying method including checking a first location of a first pattern in a layout of a stacked memory device,...
2017/0250194 SEMICONDUCTOR DEVICES INCLUDING STACKED ELECTRODES
Semiconductor devices are provided. A semiconductor device includes first and second stacks of electrodes. Moreover, the semiconductor device includes first...
2017/0250193 METHOD OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
A method of manufacturing three-dimensional semiconductor device, comprising the steps of: forming a stack structure of a plurality of a first material layers...
2017/0250192 Non-Volatile Memory With Silicided Bit Line Contacts
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in...
2017/0250191 METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE
The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an...
2017/0250190 MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus...
2017/0250189 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a...
2017/0250188 MANUFACTURING METHOD OF NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY
A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region...
2017/0250187 Anti-Fuse Memory And Semiconductor Storage Device
In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word...
2017/0250186 METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED THEREBY
A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing...
2017/0250185 DYNAMIC MEMORY STRUCTURE
A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and...
2017/0250184 SEMICONDUCTOR DEVICE
A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the...
2017/0250183 METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH SILICON AND SILICON GERMANIUM FINS
At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an...
2017/0250182 INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON
Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom...
2017/0250181 FINFET DEVICE WITH ENLARGED CHANNEL REGIONS
A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of...
2017/0250180 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel...
2017/0250179 SEMICONDUCTOR DEVICE
A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a...
2017/0250178 DECOUPLING CAPACITOR
A device is disclosed that includes active areas, gates, and conductors. The active areas are disposed apart from each other. The gates are crossing over the...
2017/0250177 SEMICONDUCTOR INTERGRATED CURCUIT APPARATUS AND MANUFACTURING METHOD FOR SAME
A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast...
2017/0250176 SILICON CONTROLLED RECTIFIER (SCR) BASED ESD PROTECTION DEVICE
The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and...
2017/0250175 LDMOS TRANSISTOR
A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a...
2017/0250174 Apparatus for Rectified RC Trigger of Back-to-Back MOS-SCR ESD Protection
An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source...
2017/0250173 VERTICAL POWER TRANSISTOR DIE WITH ETCHED BEVELED EDGES FOR INCREASING BREAKDOWN VOLTAGE
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the...
2017/0250171 SEMICONDUCTOR PACKAGE AND REWORK PROCESS FOR THE SAME
An embodiment is a method including bonding a first package to a first set of conductive pads of a second package with a first set of solder joints, testing...
2017/0250170 INTEGRATED CIRCUIT PACKAGE AND METHODS OF FORMING SAME
An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to...
2017/0250169 OPTICAL PROXIMITY SENSOR ARRANGEMENT AND METHOD FOR PRODUCING AN OPTICAL PROXIMITY SENSOR ARRANGEMENT
An optical proximity sensor arrangement comprises a semiconductor substrate (100) with a main surface (101). A first integrated circuit (200) comprises at...
2017/0250168 DISPLAY INCLUDING NANOSCALE LED MODULE
Provided are a display including a very-small light-emitting diode (LED) and a method of manufacturing the same. The display includes a panel in which a first...
2017/0250167 EFFICIENTLY MICRO-TRANSFER PRINTING MICRO-SCALE DEVICES ONTO LARGE-FORMAT SUBSTRATES
A method of making a micro-transfer printed system includes providing a source wafer having a plurality of micro-transfer printable source devices arranged at...
2017/0250166 THERMAL PERFORMANCE STRUCTURE FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME
An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die....
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