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Patent # Description
2017/0256574 Image-Sensing Device
An image-sensing device includes a semiconductor substrate including an image-sensing region and a peripheral circuit region surrounding the image-sensing...
2017/0256573 DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A display device and a method for manufacturing the same are provided. The display device includes a first substrate, a second substrate and a light curable...
2017/0256572 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Provided is a novel semiconductor device. A switching element, specifically a transistor having a well potential structure is manufactured by utilizing a...
2017/0256571 Sharing Capacitor, Pixel Having Sharing Capacitor, And Array Substrate Having Sharing Capacitor
The present invention proposes a sharing capacitor, a pixel having the sharing capacitor, and an array substrate having the sharing capacitor. The sharing...
2017/0256570 SEMICONDUCTOR DISPLAY DEVICE
It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface...
2017/0256569 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
Provided is a semiconductor device including a first transistor having an oxide semiconductor film, an interlayer film over the first transistor, and second...
2017/0256568 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap...
2017/0256567 THIN FILM TRANSISTOR ARRAY PANEL
A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer...
2017/0256566 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a first conductive layer on the substrate and including a main pattern, and substantially symmetrical auxiliary...
2017/0256565 FIELD-EFFECT TRANSISTORS WITH A NON-RELAXED STRAINED CHANNEL
Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A...
2017/0256564 VERTICAL MEMORY DEVICES
According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance...
2017/0256563 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes electrode layers stacked on a conductive layer, and columnar bodies extending in the electrode layers in a stacked...
2017/0256562 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor memory device includes forming a first insulating layer on a conductive layer; forming a second insulating layer on...
2017/0256561 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a lower layer and an etch catalyst layer which...
2017/0256560 SEMICONDUCTOR DEVICE
A surface area of a transverse cross section of an upper portion of a columnar portion is greater than a surface area of a transverse cross section of a lower...
2017/0256559 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME
A semiconductor device includes interlayer insulating layers and conductive patterns alternately stacked over a pipe gate, a first slit and a second slit...
2017/0256558 Semiconductor Memory Devices
Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region...
2017/0256557 METAL-ONO-VACUUM TUBE CHARGE TRAP FLASH (VTCTF) NONVOLATILE MEMORY AND THE METHOD FOR MAKING THE SAME
The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using ...
2017/0256556 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers,...
2017/0256555 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a memory cell array including a first memory cell provided on a substrate and a second memory cell...
2017/0256554 MANUFACTURING METHOD OF NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a conductive layer is patterned based on a first mask pattern to form word lines extending in a cell array region in a row...
2017/0256553 Method for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a...
2017/0256552 Application of Antiferroelectric Like Materials in Non-Volatile Memory Devices
Integrated devices comprising pinched hysteresis loop (PHL) materials in a capacitor or a transistor stack are disclosed. PHL materials include field induced...
2017/0256551 SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS
A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally...
2017/0256550 SRAM Cells with Vertical Gate-All-Round MOSFETS
A Static Random Access Memory (SRAM) cell includes a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched...
2017/0256549 STATIC RANDOM ACCESS MEMORY
A static random access memory (SRAM) cell includes first through fourth source diffusion regions sequentially arranged in a first direction, a first pass-gate...
2017/0256548 STATIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF
A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second...
2017/0256547 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair...
2017/0256546 SINGLE SOURCE/DRAIN EPITAXY FOR CO-INTEGRATING nFET SEMICONDUCTOR FINS AND pFET SEMICONDUCTOR FINS
A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor...
2017/0256545 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type...
2017/0256544 SEMICONDUCTOR DEVICE INCLUDING MOS TRANSISTOR
A semiconductor device including a MOS transistor is provided. The semiconductor device may include a first MOS transistor including first source/drain...
2017/0256543 WELL AND PUNCH THROUGH STOPPER FORMATION USING CONFORMAL DOPING
A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant...
2017/0256541 METHOD OF FORMING SUPER STEEP RETROGRADE WELLS ON FINFET
A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing...
2017/0256540 SEMICONDUCTOR STRUCTURE WITH LOW DEFECT AND METHOD FOR FORMING THE SAME
A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a fin...
2017/0256539 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and...
2017/0256538 HYBRID STRUCTURE WITH SEPARATE CONTROLS
A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor...
2017/0256537 MOSFET Transistors with Robust Subthreshold Operations
An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region...
2017/0256536 SEMICONDUCTOR DEVICE
A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall...
2017/0256535 SINGLE MASK LEVEL INCLUDING A RESISTOR AND A THROUGH-GATE IMPLANT
A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a...
2017/0256534 APPARATUS AND METHODS FOR ACTIVELY-CONTROLLED TRANSIENT OVERSTRESS PROTECTION WITH FALSE CONDITION SHUTDOWN
Apparatus and methods for transient overstress protection with false condition shutdown are provided herein. In certain configurations, a high-voltage tolerant...
2017/0256533 ELECTROSTATIC DISCHARGE PROTECTION DEVICE
An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer...
2017/0256532 INTEGRATED PROTECTION DEVICES WITH MONITORING OF ELECTRICAL CHARACTERISTICS
Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching...
2017/0256531 SOI INTEGRATED CIRCUIT EQUIPPED WITH A DEVICE FOR PROTECTING AGAINST ELECTROSTATIC DISCHARGES
A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty...
2017/0256530 SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION
A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The...
2017/0256529 APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT
Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are...
2017/0256528 METHODS OF MAKING SEMICONDUCTOR DEVICE PACKAGES AND RELATED SEMICONDUCTOR DEVICE PACKAGES
Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level....
2017/0256527 SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER
A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module...
2017/0256526 TARGET INTEGRATED CIRCUIT COMBINED WITH A PLURALITY OF PHOTOVOLTAIC CELLS
A microchip structure and a method for manufacturing thereof are provided. The microchip structure comprises a target integrated circuit (TIC) comprising a...
2017/0256525 LOCALIZED REDISTRIBUTION LAYER STRUCTURE FOR EMBEDDED COMPONENT PACKAGE AND METHOD
An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active...
2017/0256524 SEMICONDUCTOR DEVICE ON GLASS SUBSTRATE AND METHOD OF MAKING THE SAME
A lighting component including a plurality of die transferred to the glass substrate. The transfer occurs by positioning the glass substrate to face a first...
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