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Patent # Description
2017/0256473 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a...
2017/0256472 Manufacturing a package using plateable encapsulant
A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so...
2017/0256471 WAFER LEVEL CHIP SCALE PACKAGE HAVING CONTINUOUS THROUGH HOLE VIA CONFIGURATION AND FABRICATION METHOD THEREOF
A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device...
2017/0256470 WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
A wiring substrate includes insulating layers including a first insulating layer such that the first insulating layer is positioned at one end of the...
2017/0256469 Interconnect Monitor Utilizing Both Open And Short Detection
The present disclosure relates to semiconductor manufacturing and the teachings of the present disclosure may be embodied in a semiconductor chip with an...
2017/0256468 TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE METALIZATION
Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the...
2017/0256467 REMOVABLE SACRIFICIAL CONNECTIONS FOR SEMICONDUCTOR DEVICES
Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a...
2017/0256466 AUTOMATED OPTICAL INSPECTION OF UNIT SPECIFIC PATTERNING
An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference...
2017/0256465 METHOD AND APPARATUS TO DETERMINE A PATTERNING PROCESS PARAMETER
A method of determining overlay of a patterning process, the method including: illuminating a substrate with a radiation beam such that a beam spot on the...
2017/0256464 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
There is to provide a semiconductor device manufacturing method capable of improving reliability in a semiconductor device, including the following steps of:...
2017/0256463 ETCH METRIC SENSITIVITY FOR ENDPOINT DETECTION
Monitoring a geometric parameter value for one or more features produced on a substrate during an etch process may involve: (a) measuring optical signals...
2017/0256462 METHOD AND STRUCTURE FOR SRB ELASTIC RELAXATION
A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to...
2017/0256460 COMPLEMENTARY NANOWIRE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a...
2017/0256459 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED SPACERS
A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate....
2017/0256458 SEMICONDUCTOR DEVICES, FINFET DEVICES, AND METHODS OF FORMING THE SAME
Semiconductor devices and FinFET devices are disclosed. A substrate has first and second regions. First and second gates are on the substrate in the first...
2017/0256457 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is...
2017/0256456 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a...
2017/0256455 METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING
Methods to form multi V.sub.t channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed....
2017/0256454 WAFER PROCESSING METHOD
Disclosed herein is a wafer processing method including a cover plate providing step of providing a cover plate on the front side of a wafer to thereby form a...
2017/0256453 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE
A manufacturing method of a semiconductor package which improves productivity and can manufacture high-quality semiconductor packages is provided. The...
2017/0256452 Methods of Forming Through Substrate Interconnects
A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the...
2017/0256451 SELF-ALIGNED INTERCONNECTS
An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity...
2017/0256450 RECESS FILLING METHOD AND PROCESSING APPARATUS
There is provided a method of filling a recess with a germanium-based film composed of germanium or silicon germanium in a substrate to be processed on which...
2017/0256449 METHODS OF FORMING CONDUCTIVE STRUCTURES WITH DIFFERENT MATERIAL COMPOSITIONS IN A METALLIZATION LAYER
One illustrative method disclosed herein includes, among other things, forming a first trench and a second trench in a layer of insulating material, the first...
2017/0256448 Doping Control of Metal Nitride Films
Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film...
2017/0256447 INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE
Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the...
2017/0256446 SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL AND ELECTRONIC DESIGN AUTOMATION METHOD THEREOF
An electronic design automation method configured to automatically design a semiconductor device includes generating a site-row having a unit height based on a...
2017/0256445 INTERCONNECT STRUCTURE AND METHOD
A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert...
2017/0256444 SEMICONDUCTOR DEVICES, FINFET DEVICES AND METHODS OF FORMING THE SAME
Semiconductor devices, FinFET devices and methods of forming the same are disclosed. In accordance with some embodiments, a semiconductor device includes a...
2017/0256443 MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION
A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at...
2017/0256442 SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A SACRIFICIAL LAYER AND METHOD OF MANUFACTURE THEREOF
A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.
2017/0256441 SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF
This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a...
2017/0256440 SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF
The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate;...
2017/0256439 SEMICONDUCTOR SUBSTRATE POLISHING METHODS AND SLURRIES AND METHODS FOR MANUFACTURING SILICON ON INSULATOR...
Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles...
2017/0256438 SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF
This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a...
2017/0256437 Integrated Circuit and Method of Forming an Integrated Circuit
An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench...
2017/0256436 WAFER HANDLING ASSEMBLY
A wafer handing assembly comprising a center hub supporting a vertical non-contact lifting head and at least one radially extending and radially retracting...
2017/0256435 UNIVERSAL PROCESS KIT
The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and...
2017/0256434 WAFER HANDLING ASSEMBLY
A wafer handling assembly comprising a center hub supporting a vertical non-contact lifting head and at least one radially extending and radially retracting...
2017/0256433 APPARATUS FOR LIQUID TREATMENT OF WAFER SHAPED ARTICLES
An apparatus for treating a wafer-shaped article comprises a spin chuck configured to hold a wafer-shaped article of a predetermined diameter in a position...
2017/0256432 OVERMOLDED CHIP SCALE PACKAGE
A method of packing a semiconductor device is disclosed. The method includes placing a wafer on a carrier such that a backside of the wafer is facing up and a...
2017/0256431 SUBSTRATE SUPPORT ASSEMBLY FOR HIGH TEMPERATURE PROCESSES
An electrostatic chuck comprises a ceramic body having a top and a bottom, one or more heating elements disposed in the ceramic body, and one or more...
2017/0256430 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
Disclosed is a substrate processing apparatus including: a substrate holding unit configured to hold a substrate; a processing container configured to...
2017/0256429 SYSTEMS AND METHODS FOR DYNAMIC SEMICONDUCTOR PROCESS SCHEDULING
Embodiments of the present disclosure can help increase throughput and reduce resource conflicts and delays in semiconductor processing tools. An exemplary...
2017/0256428 Container Transport Facility
A storage portion includes a first support portion and a second support portion that support a container. The storage portion is configured to change between a...
2017/0256427 SUBSTRATE CLEANING APPARATUS, SUBSTRATE CLEANING METHOD AND NON-TRANSITORY STORAGE MEDIUM
A cleaning liquid and a gas are discharged in sequence to a central portion of a substrate while the substrate is being rotated, and after nozzles that...
2017/0256426 SUBSTRATE PROCESSING DEVICE
A substrate processing apparatus includes: a circulation pipe which defines a circulation passage through which a chemical liquid within a chemical-liquid tank...
2017/0256425 METHODS AND APPARATUS FOR CONSERVING ELECTRONIC DEVICE MANUFACTURING RESOURCES
A method for operating an electronic device manufacturing system is provided that includes introducing an inert gas into a process tool vacuum pump at a first...
2017/0256424 APPARATUS FOR PURGING SEMICONDUCTOR PROCESS CHAMBER SLIT VALVE OPENING
A semiconductor processing chamber is provided and may include a wafer transfer passage that extends through a chamber wall and has an inner passage surface...
2017/0256423 SUBSTRATE TREATING DEVICE AND SUBSTRATE TREATING METHOD
According to the embodiment, a substrate treating device 10 for treating a semiconductor wafer W using an etchant L containing hydrofluoric acid and nitric...
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